{"id":"https://openalex.org/W2116015356","doi":"https://doi.org/10.1145/1289881.1289893","title":"Performance evaluation and optimization of dual-port SDRAM architecture for mobile embedded systems","display_name":"Performance evaluation and optimization of dual-port SDRAM architecture for mobile embedded systems","publication_year":2007,"publication_date":"2007-09-30","ids":{"openalex":"https://openalex.org/W2116015356","doi":"https://doi.org/10.1145/1289881.1289893","mag":"2116015356"},"language":"en","primary_location":{"id":"doi:10.1145/1289881.1289893","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1289881.1289893","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026611490","display_name":"Hoeseok Yang","orcid":"https://orcid.org/0000-0002-7929-7470"},"institutions":[{"id":"https://openalex.org/I139264467","display_name":"Seoul National University","ror":"https://ror.org/04h9pn542","country_code":"KR","type":"education","lineage":["https://openalex.org/I139264467"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Hoeseok Yang","raw_affiliation_strings":["Seoul National University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Seoul National University","institution_ids":["https://openalex.org/I139264467"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101906662","display_name":"Sungchan Kim","orcid":"https://orcid.org/0000-0002-5887-5606"},"institutions":[{"id":"https://openalex.org/I139264467","display_name":"Seoul National University","ror":"https://ror.org/04h9pn542","country_code":"KR","type":"education","lineage":["https://openalex.org/I139264467"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Sungchan Kim","raw_affiliation_strings":["Seoul National University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Seoul National University","institution_ids":["https://openalex.org/I139264467"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039554166","display_name":"Hae-woo Park","orcid":null},"institutions":[{"id":"https://openalex.org/I139264467","display_name":"Seoul National University","ror":"https://ror.org/04h9pn542","country_code":"KR","type":"education","lineage":["https://openalex.org/I139264467"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Hae-woo Park","raw_affiliation_strings":["Seoul National University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Seoul National University","institution_ids":["https://openalex.org/I139264467"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100434594","display_name":"Jinwoo Kim","orcid":"https://orcid.org/0000-0002-2237-4965"},"institutions":[{"id":"https://openalex.org/I139264467","display_name":"Seoul National University","ror":"https://ror.org/04h9pn542","country_code":"KR","type":"education","lineage":["https://openalex.org/I139264467"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jinwoo Kim","raw_affiliation_strings":["Seoul National University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Seoul National University","institution_ids":["https://openalex.org/I139264467"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5029793438","display_name":"Soonhoi Ha","orcid":"https://orcid.org/0000-0001-7472-9142"},"institutions":[{"id":"https://openalex.org/I139264467","display_name":"Seoul National University","ror":"https://ror.org/04h9pn542","country_code":"KR","type":"education","lineage":["https://openalex.org/I139264467"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Soonhoi Ha","raw_affiliation_strings":["Seoul National University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Seoul National University","institution_ids":["https://openalex.org/I139264467"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I139264467"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"53","last_page":"57"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8155291080474854},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.5366994738578796},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5296832323074341},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.5188397169113159},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.5068214535713196},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4803841710090637},{"id":"https://openalex.org/keywords/distributed-shared-memory","display_name":"Distributed shared memory","score":0.4643799066543579},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.45302268862724304},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.44756239652633667},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.43214109539985657},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.4307229816913605},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.42070651054382324},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3645437955856323},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.2592463493347168},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.25435394048690796},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.2414911389350891},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.20488187670707703},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07939973473548889}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8155291080474854},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.5366994738578796},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5296832323074341},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.5188397169113159},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.5068214535713196},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4803841710090637},{"id":"https://openalex.org/C39528615","wikidata":"https://www.wikidata.org/wiki/Q1229610","display_name":"Distributed shared memory","level":5,"score":0.4643799066543579},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.45302268862724304},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.44756239652633667},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.43214109539985657},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.4307229816913605},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.42070651054382324},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3645437955856323},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2592463493347168},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.25435394048690796},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.2414911389350891},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.20488187670707703},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07939973473548889},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1289881.1289893","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1289881.1289893","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.46000000834465027}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1977813675","https://openalex.org/W2112804590","https://openalex.org/W2114860335","https://openalex.org/W2159064178"],"related_works":["https://openalex.org/W2148966412","https://openalex.org/W4233816696","https://openalex.org/W120214571","https://openalex.org/W1979830285","https://openalex.org/W167891743","https://openalex.org/W2181858947","https://openalex.org/W2018761720","https://openalex.org/W43633106","https://openalex.org/W2173219398","https://openalex.org/W4285245242"],"abstract_inverted_index":{"Recently":[0],"dual-port":[1],"SDRAM":[2],"(DPSDRAM)":[3],"architecture":[4],"tailored":[5],"for":[6,31],"dual-processor":[7],"based":[8],"mobile":[9],"embedded":[10],"systems":[11],"has":[12],"been":[13],"announced":[14],"where":[15],"a":[16,56,107,112],"single":[17],"memory":[18,30,38,51],"chip":[19],"plays":[20],"the":[21,24,28,49,73,87,124],"role":[22],"of":[23,43,76],"local":[25],"memories":[26],"and":[27,81,100],"shared":[29,50,88],"both":[32,44],"processors.":[33],"In":[34],"order":[35],"to":[36,48,97,123],"keep":[37],"consistency":[39],"from":[40],"simultaneous":[41,95],"accesses":[42,96],"ports,":[45],"every":[46],"access":[47,64],"should":[52],"be":[53],"protected":[54],"by":[55,71,85],"synchronization":[57],"mechanism,":[58],"which":[59],"can":[60],"result":[61,114],"in":[62],"substantial":[63],"latency.":[65],"We":[66],"propose":[67],"two":[68],"optimization":[69],"techniques":[70],"exploiting":[72],"communication":[74],"patterns":[75],"target":[77],"application:":[78],"lock-priority":[79],"scheme":[80],"static-copy":[82],"scheme.":[83],"Further,":[84],"dividing":[86],"bank":[89],"into":[90],"multiple":[91],"blocks,":[92],"we":[93,116],"enable":[94],"different":[98],"blocks":[99],"achieve":[101,117],"considerable":[102],"performance":[103,120],"gain.":[104],"Experiments":[105],"on":[106],"virtual":[108],"prototyping":[109],"system":[110],"show":[111],"promising":[113],"that":[115],"about":[118],"20-50%":[119],"gain":[121],"compared":[122],"base":[125],"DPSDRAM":[126],"architecture.":[127]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}