{"id":"https://openalex.org/W2113185708","doi":"https://doi.org/10.1145/1289881.1289889","title":"An integrated ARM and multi-core DSP simulator","display_name":"An integrated ARM and multi-core DSP simulator","publication_year":2007,"publication_date":"2007-09-30","ids":{"openalex":"https://openalex.org/W2113185708","doi":"https://doi.org/10.1145/1289881.1289889","mag":"2113185708"},"language":"en","primary_location":{"id":"doi:10.1145/1289881.1289889","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1289881.1289889","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031825368","display_name":"Sharad Singhai","orcid":null},"institutions":[{"id":"https://openalex.org/I4210113506","display_name":"Sandpiper Technologies (United States)","ror":"https://ror.org/025zjjr82","country_code":"US","type":"company","lineage":["https://openalex.org/I4210113506"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sharad Singhai","raw_affiliation_strings":["Sandbridge Technologies Inc"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sandbridge Technologies Inc","institution_ids":["https://openalex.org/I4210113506"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111438154","display_name":"Ming-Yung Ko","orcid":null},"institutions":[{"id":"https://openalex.org/I4210113506","display_name":"Sandpiper Technologies (United States)","ror":"https://ror.org/025zjjr82","country_code":"US","type":"company","lineage":["https://openalex.org/I4210113506"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"MingYung Ko","raw_affiliation_strings":["Sandbridge Technologies Inc"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sandbridge Technologies Inc","institution_ids":["https://openalex.org/I4210113506"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091099778","display_name":"Sanjay Jinturkar","orcid":null},"institutions":[{"id":"https://openalex.org/I4210113506","display_name":"Sandpiper Technologies (United States)","ror":"https://ror.org/025zjjr82","country_code":"US","type":"company","lineage":["https://openalex.org/I4210113506"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sanjay Jinturkar","raw_affiliation_strings":["Sandbridge Technologies Inc"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sandbridge Technologies Inc","institution_ids":["https://openalex.org/I4210113506"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006552382","display_name":"Mayan Moudgill","orcid":null},"institutions":[{"id":"https://openalex.org/I4210113506","display_name":"Sandpiper Technologies (United States)","ror":"https://ror.org/025zjjr82","country_code":"US","type":"company","lineage":["https://openalex.org/I4210113506"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mayan Moudgill","raw_affiliation_strings":["Sandbridge Technologies Inc"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sandbridge Technologies Inc","institution_ids":["https://openalex.org/I4210113506"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5086798411","display_name":"John Glossner","orcid":"https://orcid.org/0000-0003-0713-2105"},"institutions":[{"id":"https://openalex.org/I4210113506","display_name":"Sandpiper Technologies (United States)","ror":"https://ror.org/025zjjr82","country_code":"US","type":"company","lineage":["https://openalex.org/I4210113506"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"John Glossner","raw_affiliation_strings":["Sandbridge Technologies Inc"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sandbridge Technologies Inc","institution_ids":["https://openalex.org/I4210113506"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210113506"],"apc_list":null,"apc_paid":null,"fwci":0.8428,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.70961497,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"33","last_page":"37"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7062563300132751},{"id":"https://openalex.org/keywords/computer-architecture-simulator","display_name":"Computer architecture simulator","score":0.7054193019866943},{"id":"https://openalex.org/keywords/x86","display_name":"x86","score":0.6660902500152588},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6425678133964539},{"id":"https://openalex.org/keywords/arm-architecture","display_name":"ARM architecture","score":0.5981359481811523},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.5387687683105469},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.516732394695282},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.49645596742630005},{"id":"https://openalex.org/keywords/extensibility","display_name":"Extensibility","score":0.48486122488975525},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.4813869297504425},{"id":"https://openalex.org/keywords/instrumentation","display_name":"Instrumentation (computer programming)","score":0.46194204688072205},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.44149476289749146},{"id":"https://openalex.org/keywords/texas-instruments-davinci","display_name":"Texas Instruments DaVinci","score":0.4150416851043701},{"id":"https://openalex.org/keywords/simulation","display_name":"Simulation","score":0.39813607931137085},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.29048746824264526},{"id":"https://openalex.org/keywords/digital-signal-processor","display_name":"Digital signal processor","score":0.19712066650390625},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.15287458896636963}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7062563300132751},{"id":"https://openalex.org/C201203610","wikidata":"https://www.wikidata.org/wiki/Q5157524","display_name":"Computer architecture simulator","level":2,"score":0.7054193019866943},{"id":"https://openalex.org/C170723468","wikidata":"https://www.wikidata.org/wiki/Q182933","display_name":"x86","level":3,"score":0.6660902500152588},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6425678133964539},{"id":"https://openalex.org/C26771161","wikidata":"https://www.wikidata.org/wiki/Q16980","display_name":"ARM architecture","level":2,"score":0.5981359481811523},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.5387687683105469},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.516732394695282},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.49645596742630005},{"id":"https://openalex.org/C32833848","wikidata":"https://www.wikidata.org/wiki/Q4115054","display_name":"Extensibility","level":2,"score":0.48486122488975525},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.4813869297504425},{"id":"https://openalex.org/C118530786","wikidata":"https://www.wikidata.org/wiki/Q1134732","display_name":"Instrumentation (computer programming)","level":2,"score":0.46194204688072205},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.44149476289749146},{"id":"https://openalex.org/C45549533","wikidata":"https://www.wikidata.org/wiki/Q7707766","display_name":"Texas Instruments DaVinci","level":4,"score":0.4150416851043701},{"id":"https://openalex.org/C44154836","wikidata":"https://www.wikidata.org/wiki/Q45045","display_name":"Simulation","level":1,"score":0.39813607931137085},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.29048746824264526},{"id":"https://openalex.org/C161611012","wikidata":"https://www.wikidata.org/wiki/Q106370","display_name":"Digital signal processor","level":3,"score":0.19712066650390625},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.15287458896636963},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1289881.1289889","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1289881.1289889","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.413.4738","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.413.4738","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cecs.uci.edu/~papers/esweek07/cases/p33.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1522250664","https://openalex.org/W1555401473","https://openalex.org/W1972946779","https://openalex.org/W2017574013","https://openalex.org/W2019326155","https://openalex.org/W2047226031","https://openalex.org/W2087256755","https://openalex.org/W2098771596","https://openalex.org/W2134633067","https://openalex.org/W2163935347","https://openalex.org/W4232917671","https://openalex.org/W4239813889","https://openalex.org/W6631155369"],"related_works":["https://openalex.org/W2369102298","https://openalex.org/W3175617817","https://openalex.org/W2090939166","https://openalex.org/W2544369712","https://openalex.org/W2121788702","https://openalex.org/W2278496197","https://openalex.org/W1581821647","https://openalex.org/W2356741398","https://openalex.org/W2008450998","https://openalex.org/W2357231070"],"abstract_inverted_index":{"In":[0,51],"this":[1],"paper":[2],"we":[3],"describe":[4],"the":[5,53],"design":[6,60],"and":[7,12],"implementation":[8],"of":[9,57],"a":[10,22,46],"flexible,":[11],"extensible,":[13],"just-in-time":[14],"ARM":[15],"simulator":[16,25,31,54],"designed":[17],"to":[18],"run":[19],"cooperatively":[20],"with":[21],"multi-core":[23,48],"DSP":[24,41],"on":[26,40],"x86":[27],"hosts.":[28],"The":[29],"integrated":[30],"can":[32],"boot":[33],"ARM/Linux":[34],"alongside":[35],"another":[36],"operating":[37,49],"system":[38,59],"running":[39],"cores,":[42],"thus":[43],"truly":[44],"supporting":[45],"heterogeneous":[47],"environment.":[50],"addition,":[52],"facilitates":[55],"exploration":[56],"several":[58],"parameters":[61],"such":[62],"as":[63],"memory":[64],"latencies,":[65],"cache":[66],"organization":[67],"etc.":[68],"via":[69],"lightweight":[70],"user-defined":[71],"instrumentation.":[72]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
