{"id":"https://openalex.org/W2165683591","doi":"https://doi.org/10.1145/1289816.1289877","title":"Predator","display_name":"Predator","publication_year":2007,"publication_date":"2007-09-30","ids":{"openalex":"https://openalex.org/W2165683591","doi":"https://doi.org/10.1145/1289816.1289877","mag":"2165683591"},"language":"en","primary_location":{"id":"doi:10.1145/1289816.1289877","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1289816.1289877","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059634103","display_name":"Benny \u00c5kesson","orcid":"https://orcid.org/0000-0003-2949-2080"},"institutions":[{"id":"https://openalex.org/I83019370","display_name":"Eindhoven University of Technology","ror":"https://ror.org/02c2kyt77","country_code":"NL","type":"education","lineage":["https://openalex.org/I83019370"]}],"countries":["NL"],"is_corresponding":true,"raw_author_name":"Benny Akesson","raw_affiliation_strings":["Technische Universiteit Eindhoven, Eindhoven, Netherlands"],"affiliations":[{"raw_affiliation_string":"Technische Universiteit Eindhoven, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I83019370"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048502768","display_name":"Kees Goossens","orcid":"https://orcid.org/0000-0001-7536-4050"},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Kees Goossens","raw_affiliation_strings":["NXP Semiconductors Research & Delft University of Technology, Eindhoven, Netherlands"],"affiliations":[{"raw_affiliation_string":"NXP Semiconductors Research & Delft University of Technology, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I98358874"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5089067115","display_name":"Markus Ringhofer","orcid":null},"institutions":[{"id":"https://openalex.org/I4092182","display_name":"Graz University of Technology","ror":"https://ror.org/00d7xrm67","country_code":"AT","type":"education","lineage":["https://openalex.org/I4092182"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Markus Ringhofer","raw_affiliation_strings":["Graz University of Technology, Graz, Austria"],"affiliations":[{"raw_affiliation_string":"Graz University of Technology, Graz, Austria","institution_ids":["https://openalex.org/I4092182"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5059634103"],"corresponding_institution_ids":["https://openalex.org/I83019370"],"apc_list":null,"apc_paid":null,"fwci":10.1039,"has_fulltext":false,"cited_by_count":214,"citation_normalized_percentile":{"value":0.98330293,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":96,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"251","last_page":"256"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7748469114303589},{"id":"https://openalex.org/keywords/arbiter","display_name":"Arbiter","score":0.7013840079307556},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.677562952041626},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.6375622749328613},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5705648064613342},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.523673951625824},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.5135865211486816},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5129403471946716},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.43882253766059875},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.42970651388168335},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.4232426881790161},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.4120231866836548},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3075349032878876},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.22433212399482727},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.21148395538330078},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.17668545246124268},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.15334415435791016}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7748469114303589},{"id":"https://openalex.org/C2779971761","wikidata":"https://www.wikidata.org/wiki/Q629872","display_name":"Arbiter","level":2,"score":0.7013840079307556},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.677562952041626},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.6375622749328613},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5705648064613342},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.523673951625824},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.5135865211486816},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5129403471946716},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.43882253766059875},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.42970651388168335},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.4232426881790161},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.4120231866836548},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3075349032878876},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.22433212399482727},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.21148395538330078},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.17668545246124268},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.15334415435791016},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1289816.1289877","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1289816.1289877","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1525290785","https://openalex.org/W1531861918","https://openalex.org/W1725472669","https://openalex.org/W2110398403","https://openalex.org/W2115172404","https://openalex.org/W2120538858","https://openalex.org/W2127140660","https://openalex.org/W2127322963","https://openalex.org/W2148439886","https://openalex.org/W2155303087","https://openalex.org/W2156139954","https://openalex.org/W2167160754","https://openalex.org/W2167195657","https://openalex.org/W2167240608","https://openalex.org/W2168072991","https://openalex.org/W2170954333","https://openalex.org/W2607411116","https://openalex.org/W3182316278","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W3008068282","https://openalex.org/W2065759842","https://openalex.org/W2557931434","https://openalex.org/W2148966412","https://openalex.org/W4285245242","https://openalex.org/W2181858947","https://openalex.org/W1979830285","https://openalex.org/W4233816696","https://openalex.org/W1707075782","https://openalex.org/W2210325884"],"abstract_inverted_index":{"Memory":[0],"requirements":[1,31,74],"of":[2,26,80,124,168,175,187,192,203],"intellectual":[3],"property":[4],"components":[5],"(IP)":[6],"in":[7,218],"contemporary":[8],"multi-processor":[9],"systems-on-chip":[10],"are":[11,21,75],"increasing.":[12],"Large":[13],"high-speed":[14],"external":[15],"memories,":[16],"such":[17,145],"as":[18],"DDR2":[19],"SDRAMs,":[20],"shared":[22],"between":[23],"a":[24,33,84,90,95,106,133,151,172,188],"multitude":[25],"IPs":[27],"to":[28,54,69,99,110,121,138,157],"satisfy":[29],"these":[30,140],"at":[32,64,143,211],"low":[34],"cost":[35],"per":[36],"bit.":[37],"However,":[38],"SDRAMs":[39],"have":[40],"highly":[41],"variable":[42],"access":[43,118],"times":[44],"that":[45,71,88,146,179],"depend":[46],"on":[47],"previous":[48],"requests.":[49],"This":[50,102],"makes":[51],"it":[52],"difficult":[53],"accurately":[55],"and":[56,60,67,94,130,150,164,197,214],"analytically":[57],"determine":[58],"latencies":[59],"the":[61,100,158,184,193,201],"useful":[62],"bandwidth":[63,93,149],"design":[65,87],"time,":[66],"hence":[68],"guarantee":[70],"hard":[72],"real-time":[73],"met.":[76],"The":[77,160,190],"main":[78],"contribution":[79],"this":[81],"paper":[82],"is":[83,103,136,155,162,180,195],"memory":[85,117,177],"controller":[86,178],"provides":[89],"guaranteed":[91,156],"minimum":[92],"maximum":[96,152],"latency":[97,153],"bound":[98,154],"IPs.":[101,159,204],"accomplished":[104],"using":[105],"novel":[107],"two-step":[108],"approach":[109,161],"predictable":[111,134],"SDRAM":[112,125],"sharing.":[113],"First,":[114],"we":[115],"define":[116],"groups,":[119],"corresponding":[120],"precomputed":[122],"sequences":[123],"commands,":[126],"with":[127,200,207],"known":[128],"efficiency":[129],"latency.":[131],"Second,":[132],"arbiter":[135],"used":[137],"schedule":[139],"groups":[141],"dynamically":[142],"run-time,":[144],"an":[147],"allocated":[148],"general":[163],"covers":[165],"all":[166],"generations":[167],"SDRAM.":[169],"We":[170],"present":[171],"modular":[173],"implementation":[174,194],"our":[176],"efficiently":[181],"integrated":[182],"into":[183],"network":[185],"interface":[186],"network-on-chip.":[189],"area":[191],"cheap,":[196],"scales":[198],"linearly":[199],"number":[202],"An":[205],"instance":[206],"six":[208],"ports":[209],"runs":[210],"200":[212],"MHz":[213],"requires":[215],"0.042":[216],"mm2":[217],"0.13\u03bcm":[219],"CMOS":[220],"technology.":[221]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":6},{"year":2021,"cited_by_count":7},{"year":2020,"cited_by_count":7},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":13},{"year":2017,"cited_by_count":6},{"year":2016,"cited_by_count":19},{"year":2015,"cited_by_count":26},{"year":2014,"cited_by_count":29},{"year":2013,"cited_by_count":20},{"year":2012,"cited_by_count":25}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2016-06-24T00:00:00"}