{"id":"https://openalex.org/W2163997673","doi":"https://doi.org/10.1145/1283780.1283822","title":"Variable-latency adder (VL-adder)","display_name":"Variable-latency adder (VL-adder)","publication_year":2007,"publication_date":"2007-08-27","ids":{"openalex":"https://openalex.org/W2163997673","doi":"https://doi.org/10.1145/1283780.1283822","mag":"2163997673"},"language":"en","primary_location":{"id":"doi:10.1145/1283780.1283822","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1283780.1283822","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2007 international symposium on Low power electronics and design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5058073627","display_name":"Yiran Chen","orcid":"https://orcid.org/0000-0002-1486-8412"},"institutions":[{"id":"https://openalex.org/I131787340","display_name":"Seagate (United States)","ror":"https://ror.org/04p1xtv71","country_code":"US","type":"company","lineage":["https://openalex.org/I131787340"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Yiran Chen","raw_affiliation_strings":["Seagate Technology"],"affiliations":[{"raw_affiliation_string":"Seagate Technology","institution_ids":["https://openalex.org/I131787340"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035225490","display_name":"Hai Li","orcid":"https://orcid.org/0000-0001-7668-569X"},"institutions":[{"id":"https://openalex.org/I131787340","display_name":"Seagate (United States)","ror":"https://ror.org/04p1xtv71","country_code":"US","type":"company","lineage":["https://openalex.org/I131787340"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hai Li","raw_affiliation_strings":["Seagate Technology"],"affiliations":[{"raw_affiliation_string":"Seagate Technology","institution_ids":["https://openalex.org/I131787340"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100626667","display_name":"Jing Li","orcid":"https://orcid.org/0000-0001-5139-938X"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jing Li","raw_affiliation_strings":["Purdue University"],"affiliations":[{"raw_affiliation_string":"Purdue University","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110204557","display_name":"Cheng\u2010Kok Koh","orcid":null},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Cheng-Kok Koh","raw_affiliation_strings":["Purdue University"],"affiliations":[{"raw_affiliation_string":"Purdue University","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5058073627"],"corresponding_institution_ids":["https://openalex.org/I131787340"],"apc_list":null,"apc_paid":null,"fwci":2.1074,"has_fulltext":false,"cited_by_count":22,"citation_normalized_percentile":{"value":0.88026095,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"195","last_page":"200"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9596354961395264},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5844036340713501},{"id":"https://openalex.org/keywords/negative-bias-temperature-instability","display_name":"Negative-bias temperature instability","score":0.5575279593467712},{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.5324455499649048},{"id":"https://openalex.org/keywords/serial-binary-adder","display_name":"Serial binary adder","score":0.4955085515975952},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4738616943359375},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4737623333930969},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.46882909536361694},{"id":"https://openalex.org/keywords/circuit-reliability","display_name":"Circuit reliability","score":0.4532318413257599},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44143998622894287},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4239412248134613},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.30877619981765747},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2750142812728882},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.23933130502700806},{"id":"https://openalex.org/keywords/threshold-voltage","display_name":"Threshold voltage","score":0.23492184281349182},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21505099534988403},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07849040627479553}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9596354961395264},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5844036340713501},{"id":"https://openalex.org/C557185","wikidata":"https://www.wikidata.org/wiki/Q6987194","display_name":"Negative-bias temperature instability","level":5,"score":0.5575279593467712},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.5324455499649048},{"id":"https://openalex.org/C116206932","wikidata":"https://www.wikidata.org/wiki/Q7454686","display_name":"Serial binary adder","level":4,"score":0.4955085515975952},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4738616943359375},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4737623333930969},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.46882909536361694},{"id":"https://openalex.org/C2778309119","wikidata":"https://www.wikidata.org/wiki/Q5121614","display_name":"Circuit reliability","level":4,"score":0.4532318413257599},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44143998622894287},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4239412248134613},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.30877619981765747},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2750142812728882},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.23933130502700806},{"id":"https://openalex.org/C195370968","wikidata":"https://www.wikidata.org/wiki/Q1754002","display_name":"Threshold voltage","level":4,"score":0.23492184281349182},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21505099534988403},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07849040627479553},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1283780.1283822","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1283780.1283822","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2007 international symposium on Low power electronics and design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.9100000262260437}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W2094662129","https://openalex.org/W2101686625","https://openalex.org/W2108890336","https://openalex.org/W2115686854","https://openalex.org/W2122507955","https://openalex.org/W2124222584","https://openalex.org/W2157024459","https://openalex.org/W2161537396","https://openalex.org/W3103339143","https://openalex.org/W4238531044","https://openalex.org/W4300103836"],"related_works":["https://openalex.org/W1999919743","https://openalex.org/W2081382200","https://openalex.org/W2364181090","https://openalex.org/W2100282217","https://openalex.org/W2157278395","https://openalex.org/W2164047446","https://openalex.org/W2096191509","https://openalex.org/W3033168326","https://openalex.org/W4299002946","https://openalex.org/W2164178706"],"abstract_inverted_index":{"Negative":[0],"bias":[1],"temperature":[2],"instability":[3],"(NBTI)":[4],"has":[5],"become":[6],"a":[7,55],"dominant":[8],"reliability":[9],"concern":[10],"for":[11,24],"nanoscale":[12],"PMOS":[13],"transistors.":[14],"In":[15],"this":[16],"paper,":[17],"we":[18],"propose":[19],"variable-latency":[20],"adder":[21,79],"(VL-adder)":[22],"technique":[23,82],"NBTI":[25],"tolerance.":[26],"By":[27],"detecting":[28],"the":[29,33,63,89],"circuit":[30],"failure":[31],"on-the-fly,":[32],"proposed":[34],"VL-adder":[35,52,81],"can":[36],"automatically":[37],"shift":[38],"data":[39],"capturing":[40],"clock":[41,60],"edge":[42],"to":[43,75],"tolerate":[44],"NBTI-induced":[45],"delay":[46],"degradation":[47,97],"on":[48],"critical":[49],"timing":[50],"paths.":[51],"operates":[53],"with":[54,93],"fixed":[56],"supply":[57],"voltage":[58],"and":[59,66],"period,":[61],"avoiding":[62],"high":[64],"design":[65],"manufacturing":[67],"costs":[68],"incurred":[69],"by":[70],"existing":[71],"NBTI-tolerant":[72],"techniques.":[73],"Compared":[74],"other":[76],"related":[77],"lower-power":[78],"designs,":[80],"always":[83],"provides":[84],"better":[85],"energy":[86],"efficiency":[87],"through":[88],"whole":[90],"chip":[91],"lifetime":[92],"very":[94],"limited":[95],"performance":[96],"(4.6%":[98],"or":[99],"less).":[100]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
