{"id":"https://openalex.org/W2103643733","doi":"https://doi.org/10.1145/1283780.1283795","title":"Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution","display_name":"Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution","publication_year":2007,"publication_date":"2007-08-27","ids":{"openalex":"https://openalex.org/W2103643733","doi":"https://doi.org/10.1145/1283780.1283795","mag":"2103643733"},"language":"en","primary_location":{"id":"doi:10.1145/1283780.1283795","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1283780.1283795","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2007 international symposium on Low power electronics and design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081512326","display_name":"Sherif Abdulkader Tawfik","orcid":"https://orcid.org/0000-0003-3592-1419"},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Sherif A. Tawfik","raw_affiliation_strings":["University of Wisconsin-Madison","Dept. of Electr. & Comput. Eng., Univ. of Wisconsin Madison, Madison, WI, USA"],"affiliations":[{"raw_affiliation_string":"University of Wisconsin-Madison","institution_ids":["https://openalex.org/I135310074"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of Wisconsin Madison, Madison, WI, USA","institution_ids":["https://openalex.org/I135310074"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5042147600","display_name":"Volkan Kursun","orcid":"https://orcid.org/0000-0002-8050-1774"},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Volkan Kursun","raw_affiliation_strings":["University of Wisconsin-Madison","Dept. of Electr. & Comput. Eng., Univ. of Wisconsin Madison, Madison, WI, USA"],"affiliations":[{"raw_affiliation_string":"University of Wisconsin-Madison","institution_ids":["https://openalex.org/I135310074"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of Wisconsin Madison, Madison, WI, USA","institution_ids":["https://openalex.org/I135310074"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5081512326"],"corresponding_institution_ids":["https://openalex.org/I135310074"],"apc_list":null,"apc_paid":null,"fwci":0.7176,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.74705931,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"62","last_page":"67"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.669183075428009},{"id":"https://openalex.org/keywords/cpu-core-voltage","display_name":"CPU core voltage","score":0.61906498670578},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.5365458130836487},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4797143340110779},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.47952723503112793},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.47250521183013916},{"id":"https://openalex.org/keywords/frequency-multiplier","display_name":"Frequency multiplier","score":0.4660773277282715},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4542437791824341},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.45086321234703064},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.4443592131137848},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.39821720123291016},{"id":"https://openalex.org/keywords/dropout-voltage","display_name":"Dropout voltage","score":0.33876532316207886},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.33002108335494995},{"id":"https://openalex.org/keywords/voltage-divider","display_name":"Voltage divider","score":0.31553205847740173},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.31382399797439575},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.308310866355896},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.18432989716529846},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11914834380149841}],"concepts":[{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.669183075428009},{"id":"https://openalex.org/C55038917","wikidata":"https://www.wikidata.org/wiki/Q453979","display_name":"CPU core voltage","level":5,"score":0.61906498670578},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.5365458130836487},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4797143340110779},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.47952723503112793},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.47250521183013916},{"id":"https://openalex.org/C146002875","wikidata":"https://www.wikidata.org/wiki/Q1074289","display_name":"Frequency multiplier","level":3,"score":0.4660773277282715},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4542437791824341},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.45086321234703064},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.4443592131137848},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.39821720123291016},{"id":"https://openalex.org/C15032970","wikidata":"https://www.wikidata.org/wiki/Q851210","display_name":"Dropout voltage","level":4,"score":0.33876532316207886},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.33002108335494995},{"id":"https://openalex.org/C49324399","wikidata":"https://www.wikidata.org/wiki/Q466758","display_name":"Voltage divider","level":3,"score":0.31553205847740173},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.31382399797439575},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.308310866355896},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.18432989716529846},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11914834380149841}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1283780.1283795","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1283780.1283795","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2007 international symposium on Low power electronics and design","raw_type":"proceedings-article"},{"id":"pmh:oai:repository.hkust.edu.hk:1783.1-41351","is_oa":false,"landing_page_url":"http://repository.hkust.edu.hk/ir/Record/1783.1-41351","pdf_url":null,"source":{"id":"https://openalex.org/S4306401796","display_name":"Rare & Special e-Zone (The Hong Kong University of Science and Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I200769079","host_organization_name":"Hong Kong University of Science and Technology","host_organization_lineage":["https://openalex.org/I200769079"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference paper"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8999999761581421,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W274004780","https://openalex.org/W1490763633","https://openalex.org/W1511935823","https://openalex.org/W1514437667","https://openalex.org/W1518236483","https://openalex.org/W1938797020","https://openalex.org/W1963803660","https://openalex.org/W2099250769","https://openalex.org/W2109730008","https://openalex.org/W2121169595","https://openalex.org/W2153903472","https://openalex.org/W2158881717","https://openalex.org/W2159699330","https://openalex.org/W2496254462","https://openalex.org/W6640483298"],"related_works":["https://openalex.org/W2559451387","https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2040807843","https://openalex.org/W3006003651","https://openalex.org/W4249038728","https://openalex.org/W2495024767","https://openalex.org/W2474747038","https://openalex.org/W2981406251","https://openalex.org/W2954620240"],"abstract_inverted_index":{"A":[0,102],"methodology":[1],"based":[2],"on":[3],"supply":[4,37,43,55,158],"voltage":[5,38,44,56,83,108,159],"and":[6,14,39,65,116,128,144],"frequency":[7,63,92,105],"scaling":[8],"for":[9,78],"lowering":[10],"the":[11,53,72,75,80,88,97,100,132,156,161],"power":[12,118,129],"consumption":[13,119,130],"temperature":[15,113,124],"fluctuations":[16,114,125],"induced":[17,126],"skew":[18,48,127],"of":[19,74,99,131],"clock":[20,29,47,76,85,91,135,164],"distribution":[21,136,152],"networks":[22],"is":[23,31,49,121],"proposed":[24,133],"in":[25,57,93],"this":[26],"paper.":[27],"The":[28,41,123],"signal":[30,86],"distributed":[32],"globally":[33],"at":[34,71,155],"a":[35,58,150],"scaled":[36],"frequency.":[40,165],"optimum":[42],"that":[45],"minimizes":[46],"44%":[50],"less":[51],"than":[52],"nominal":[54,157],"0.18\u03bcm":[59],"CMOS":[60],"technology.":[61],"Combined":[62],"multiplier":[64],"level":[66,109],"converter":[67],"circuits":[68],"are":[69,138],"utilized":[70],"leaves":[73],"tree":[77],"restoring":[79],"standard":[81,151],"full":[82],"swing":[84],"with":[87,107,160],"higher":[89],"target":[90,162],"order":[94],"to":[95,142,149],"maintain":[96],"performance":[98],"system.":[101],"novel":[103],"dual-threshold-voltage":[104],"doubler":[106],"conversion":[110],"capability,":[111],"suppressed":[112],"sensitivity,":[115],"low":[117],"characteristics":[120],"presented.":[122],"dual-VDD/dual-frequency":[134],"network":[137,153],"reduced":[139],"by":[140],"up":[141],"80%":[143],"76%,":[145],"respectively,":[146],"as":[147],"compared":[148],"operating":[154],"system":[163]},"counts_by_year":[{"year":2014,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}