{"id":"https://openalex.org/W2097840688","doi":"https://doi.org/10.1145/1283780.1283789","title":"Energy efficient near-threshold chip multi-processing","display_name":"Energy efficient near-threshold chip multi-processing","publication_year":2007,"publication_date":"2007-08-27","ids":{"openalex":"https://openalex.org/W2097840688","doi":"https://doi.org/10.1145/1283780.1283789","mag":"2097840688"},"language":"en","primary_location":{"id":"doi:10.1145/1283780.1283789","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1283780.1283789","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2007 international symposium on Low power electronics and design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102307959","display_name":"Bo Zhai","orcid":null},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan\u2013Ann Arbor","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Bo Zhai","raw_affiliation_strings":["University of Michigan","University of Michigan Ann Arbor MI, USA"],"affiliations":[{"raw_affiliation_string":"University of Michigan","institution_ids":["https://openalex.org/I27837315"]},{"raw_affiliation_string":"University of Michigan Ann Arbor MI, USA","institution_ids":["https://openalex.org/I27837315"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014250626","display_name":"Ronald Dreslinski","orcid":null},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan\u2013Ann Arbor","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ronald G. Dreslinski","raw_affiliation_strings":["University of Michigan","University of Michigan Ann Arbor MI, USA"],"affiliations":[{"raw_affiliation_string":"University of Michigan","institution_ids":["https://openalex.org/I27837315"]},{"raw_affiliation_string":"University of Michigan Ann Arbor MI, USA","institution_ids":["https://openalex.org/I27837315"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026311377","display_name":"David Blaauw","orcid":"https://orcid.org/0000-0001-6744-7075"},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan\u2013Ann Arbor","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Blaauw","raw_affiliation_strings":["University of Michigan","University of Michigan Ann Arbor MI, USA"],"affiliations":[{"raw_affiliation_string":"University of Michigan","institution_ids":["https://openalex.org/I27837315"]},{"raw_affiliation_string":"University of Michigan Ann Arbor MI, USA","institution_ids":["https://openalex.org/I27837315"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037541525","display_name":"Trevor Mudge","orcid":"https://orcid.org/0000-0001-7845-2187"},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan\u2013Ann Arbor","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Trevor Mudge","raw_affiliation_strings":["University of Michigan","University of Michigan Ann Arbor MI, USA"],"affiliations":[{"raw_affiliation_string":"University of Michigan","institution_ids":["https://openalex.org/I27837315"]},{"raw_affiliation_string":"University of Michigan Ann Arbor MI, USA","institution_ids":["https://openalex.org/I27837315"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000767141","display_name":"Dennis Sylvester","orcid":"https://orcid.org/0000-0003-2598-0458"},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan\u2013Ann Arbor","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dennis Sylvester","raw_affiliation_strings":["University of Michigan","University of Michigan Ann Arbor MI, USA"],"affiliations":[{"raw_affiliation_string":"University of Michigan","institution_ids":["https://openalex.org/I27837315"]},{"raw_affiliation_string":"University of Michigan Ann Arbor MI, USA","institution_ids":["https://openalex.org/I27837315"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5102307959"],"corresponding_institution_ids":["https://openalex.org/I27837315"],"apc_list":null,"apc_paid":null,"fwci":8.5771,"has_fulltext":false,"cited_by_count":98,"citation_normalized_percentile":{"value":0.97782875,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"32","last_page":"37"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/subthreshold-conduction","display_name":"Subthreshold conduction","score":0.876577615737915},{"id":"https://openalex.org/keywords/efficient-energy-use","display_name":"Efficient energy use","score":0.7556153535842896},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7323871850967407},{"id":"https://openalex.org/keywords/threshold-voltage","display_name":"Threshold voltage","score":0.5449749827384949},{"id":"https://openalex.org/keywords/energy","display_name":"Energy (signal processing)","score":0.5434619784355164},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5350571274757385},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5279729962348938},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.46967703104019165},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4314592480659485},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3974630534648895},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.39692550897598267},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.35165196657180786},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.33112990856170654},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.27891093492507935},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.24477636814117432},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15705284476280212},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.112328439950943}],"concepts":[{"id":"https://openalex.org/C156465305","wikidata":"https://www.wikidata.org/wiki/Q1658601","display_name":"Subthreshold conduction","level":4,"score":0.876577615737915},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.7556153535842896},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7323871850967407},{"id":"https://openalex.org/C195370968","wikidata":"https://www.wikidata.org/wiki/Q1754002","display_name":"Threshold voltage","level":4,"score":0.5449749827384949},{"id":"https://openalex.org/C186370098","wikidata":"https://www.wikidata.org/wiki/Q442787","display_name":"Energy (signal processing)","level":2,"score":0.5434619784355164},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5350571274757385},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5279729962348938},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.46967703104019165},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4314592480659485},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3974630534648895},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.39692550897598267},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.35165196657180786},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.33112990856170654},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.27891093492507935},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.24477636814117432},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15705284476280212},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.112328439950943},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1283780.1283789","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1283780.1283789","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2007 international symposium on Low power electronics and design","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.648.6536","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.648.6536","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://web.eecs.umich.edu/~tnm/trev_test/papersPDF/2007.08.Energy Efficient Near threshold Chip Multi processing_ISLPED 2007.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.9100000262260437}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1491082069","https://openalex.org/W1607087355","https://openalex.org/W1968597908","https://openalex.org/W2002038549","https://openalex.org/W2017195664","https://openalex.org/W2044206819","https://openalex.org/W2111372718","https://openalex.org/W2127190809","https://openalex.org/W2128748528","https://openalex.org/W2134067926","https://openalex.org/W2139928929","https://openalex.org/W2140823559","https://openalex.org/W2145021036","https://openalex.org/W2151037583","https://openalex.org/W2156638740"],"related_works":["https://openalex.org/W2009852498","https://openalex.org/W3004587385","https://openalex.org/W1991521745","https://openalex.org/W2109147260","https://openalex.org/W2786811717","https://openalex.org/W4220771873","https://openalex.org/W2069364674","https://openalex.org/W2062767191","https://openalex.org/W2117738807","https://openalex.org/W4231458110"],"abstract_inverted_index":{"Subthreshold":[0],"circuit":[1],"design":[2],"has":[3],"become":[4],"a":[5,74,103,115],"popular":[6],"approach":[7,111],"for":[8,81],"building":[9],"energy":[10,44,82,105],"efficient":[11],"digital":[12],"circuits.":[13],"One":[14],"drawback":[15],"is":[16,79],"performance":[17,34,48],"degradation":[18],"due":[19],"to":[20,31,52,58],"the":[21,42,108],"exponentially":[22],"reduced":[23],"driving":[24],"current.":[25],"This":[26],"had":[27],"limited":[28],"subthreshold":[29,54],"circuits":[30],"relatively":[32],"low":[33],"applications":[35],"such":[36],"as":[37],"sensor":[38],"networks.":[39],"To":[40],"retain":[41],"excellent":[43],"efficiency":[45],"while":[46],"reducing":[47],"loss,":[49],"we":[50],"propose":[51],"apply":[53],"and":[55,87,94],"near-threshold":[56],"techniques":[57],"chip":[59],"multi-processors.":[60],"We":[61],"show":[62,101],"that":[63],"an":[64],"architecture":[65],"where":[66],"several":[67],"slower":[68],"cores":[69,86],"are":[70],"clustered":[71],"together":[72],"with":[73],"shared":[75],"faster":[76],"L1":[77],"cache":[78],"optimal":[80],"efficiency,":[83],"because":[84],"processor":[85],"memory":[88],"operate":[89],"best":[90],"at":[91],"different":[92],"supply":[93],"threshold":[95],"voltages.":[96],"In":[97],"particular,":[98],"SPLASH2":[99],"benchmarks":[100],"about":[102],"53%":[104],"improvement":[106],"over":[107,114],"traditional":[109],"CMP":[110],"(about":[112],"70%":[113],"single":[116],"core":[117],"machine).":[118]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":5},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":7},{"year":2017,"cited_by_count":11},{"year":2016,"cited_by_count":9},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":9},{"year":2012,"cited_by_count":10}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}