{"id":"https://openalex.org/W2097452558","doi":"https://doi.org/10.1145/1278480.1278496","title":"IPR","display_name":"IPR","publication_year":2007,"publication_date":"2007-01-01","ids":{"openalex":"https://openalex.org/W2097452558","doi":"https://doi.org/10.1145/1278480.1278496","mag":"2097452558"},"language":"en","primary_location":{"id":"doi:10.1145/1278480.1278496","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1278480.1278496","pdf_url":null,"source":{"id":"https://openalex.org/S4210231368","display_name":"Proceedings - ACM IEEE Design Automation Conference","issn_l":"0738-100X","issn":["0738-100X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 44th annual conference on Design automation - DAC '07","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113424838","display_name":"Min Pan","orcid":"https://orcid.org/0000-0002-2552-1086"},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Min Pan","raw_affiliation_strings":["Cadence Design Systems, Inc., San Jose, CA","Cadence Design Systems Inc., San Jose, CA"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, Inc., San Jose, CA","institution_ids":["https://openalex.org/I66217453"]},{"raw_affiliation_string":"Cadence Design Systems Inc., San Jose, CA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101613339","display_name":"Chris Chu","orcid":"https://orcid.org/0000-0001-6073-1719"},"institutions":[{"id":"https://openalex.org/I173911158","display_name":"Iowa State University","ror":"https://ror.org/04rswrd78","country_code":"US","type":"education","lineage":["https://openalex.org/I173911158"]},{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chris Chu","raw_affiliation_strings":["Iowa State University, Ames, IA","Cadence Design Syst. Inc., San Jose"],"affiliations":[{"raw_affiliation_string":"Iowa State University, Ames, IA","institution_ids":["https://openalex.org/I173911158"]},{"raw_affiliation_string":"Cadence Design Syst. Inc., San Jose","institution_ids":["https://openalex.org/I66217453"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5113424838"],"corresponding_institution_ids":["https://openalex.org/I66217453"],"apc_list":null,"apc_paid":null,"fwci":5.4004,"has_fulltext":false,"cited_by_count":77,"citation_normalized_percentile":{"value":0.95384174,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"59","last_page":"59"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.8628408908843994},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7067000865936279},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6746766567230225},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6512660384178162},{"id":"https://openalex.org/keywords/network-routing","display_name":"Network routing","score":0.4334699213504791},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.41395044326782227},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3397529721260071},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.32129591703414917},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.31227394938468933},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2962387800216675},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.2784161865711212},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.09401008486747742}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.8628408908843994},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7067000865936279},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6746766567230225},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6512660384178162},{"id":"https://openalex.org/C2983435990","wikidata":"https://www.wikidata.org/wiki/Q22725","display_name":"Network routing","level":3,"score":0.4334699213504791},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.41395044326782227},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3397529721260071},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.32129591703414917},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.31227394938468933},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2962387800216675},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.2784161865711212},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.09401008486747742}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1278480.1278496","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1278480.1278496","pdf_url":null,"source":{"id":"https://openalex.org/S4210231368","display_name":"Proceedings - ACM IEEE Design Automation Conference","issn_l":"0738-100X","issn":["0738-100X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 44th annual conference on Design automation - DAC '07","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1542046229","https://openalex.org/W1603813963","https://openalex.org/W2025082082","https://openalex.org/W2085073472","https://openalex.org/W2114136290","https://openalex.org/W2120315922","https://openalex.org/W2137890965","https://openalex.org/W2155462145","https://openalex.org/W2156954556","https://openalex.org/W2163961680","https://openalex.org/W2173896496","https://openalex.org/W2178255440"],"related_works":["https://openalex.org/W1571681534","https://openalex.org/W1974474301","https://openalex.org/W2155675690","https://openalex.org/W1980984060","https://openalex.org/W2135858590","https://openalex.org/W4205718258","https://openalex.org/W2059364457","https://openalex.org/W2353466952","https://openalex.org/W4256717873","https://openalex.org/W1989674257"],"abstract_inverted_index":{"In":[0,67],"nanometer-scale":[1],"VLSI":[2],"technologies,":[3],"several":[4],"interconnect":[5,11,29,40,57],"issues":[6],"like":[7],"routing":[8,44],"congestion":[9],"and":[10,76],"delay":[12],"have":[13],"become":[14],"the":[15,38,43,69],"main":[16],"concerns":[17],"in":[18,42],"placement.":[19,32],"However,":[20],"all":[21],"previous":[22],"placement":[23,49,70],"approaches":[24],"optimize":[25],"some":[26],"very":[27],"primitive":[28,56],"models":[30,34,58],"during":[31],"These":[33],"are":[35],"far":[36],"from":[37],"actual":[39],"implementation":[41],"stage.":[45],"As":[46],"a":[47],"result,":[48],"solution":[50],"considered":[51],"to":[52,62],"be":[53,63,74,81],"good":[54],"by":[55],"may":[59,71,79],"turn":[60],"out":[61],"poor":[64],"after":[65],"routing.":[66],"addition,":[68],"not":[72,80],"even":[73],"routable":[75],"timing":[77],"closure":[78],"achievable.":[82]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":6},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":5},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":10},{"year":2012,"cited_by_count":9}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2016-06-24T00:00:00"}
