{"id":"https://openalex.org/W2138843457","doi":"https://doi.org/10.1145/1278349.1278364","title":"Compilation for compact power-gating controls","display_name":"Compilation for compact power-gating controls","publication_year":2007,"publication_date":"2007-09-01","ids":{"openalex":"https://openalex.org/W2138843457","doi":"https://doi.org/10.1145/1278349.1278364","mag":"2138843457"},"language":"en","primary_location":{"id":"doi:10.1145/1278349.1278364","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1278349.1278364","pdf_url":null,"source":{"id":"https://openalex.org/S105046310","display_name":"ACM Transactions on Design Automation of Electronic Systems","issn_l":"1084-4309","issn":["1084-4309","1557-7309"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Design Automation of Electronic Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059393275","display_name":"Yi\u2010Ping You","orcid":"https://orcid.org/0000-0002-4455-3147"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Yi-Ping You","raw_affiliation_strings":["National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009835723","display_name":"Chung-Wen Huang","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chung-Wen Huang","raw_affiliation_strings":["National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110037994","display_name":"Jenq Kuen Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jenq Kuen Lee","raw_affiliation_strings":["National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5059393275"],"corresponding_institution_ids":["https://openalex.org/I25846049"],"apc_list":null,"apc_paid":null,"fwci":0.9548,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.78298727,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"12","issue":"4","first_page":"51","last_page":"51"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.8599275350570679},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8525195121765137},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.5880100727081299},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.49283337593078613},{"id":"https://openalex.org/keywords/gating","display_name":"Gating","score":0.4918694496154785},{"id":"https://openalex.org/keywords/merge","display_name":"Merge (version control)","score":0.4337795376777649},{"id":"https://openalex.org/keywords/optimizing-compiler","display_name":"Optimizing compiler","score":0.4326595366001129},{"id":"https://openalex.org/keywords/instruction-scheduling","display_name":"Instruction scheduling","score":0.43045663833618164},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.40445002913475037},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3112412095069885},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.17283207178115845},{"id":"https://openalex.org/keywords/dynamic-priority-scheduling","display_name":"Dynamic priority scheduling","score":0.14353609085083008},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13931435346603394},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.12622395157814026},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.12012529373168945}],"concepts":[{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.8599275350570679},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8525195121765137},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.5880100727081299},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.49283337593078613},{"id":"https://openalex.org/C194544171","wikidata":"https://www.wikidata.org/wiki/Q21105679","display_name":"Gating","level":2,"score":0.4918694496154785},{"id":"https://openalex.org/C197129107","wikidata":"https://www.wikidata.org/wiki/Q1921621","display_name":"Merge (version control)","level":2,"score":0.4337795376777649},{"id":"https://openalex.org/C190902152","wikidata":"https://www.wikidata.org/wiki/Q1325106","display_name":"Optimizing compiler","level":3,"score":0.4326595366001129},{"id":"https://openalex.org/C73564150","wikidata":"https://www.wikidata.org/wiki/Q11417093","display_name":"Instruction scheduling","level":5,"score":0.43045663833618164},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.40445002913475037},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3112412095069885},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.17283207178115845},{"id":"https://openalex.org/C107568181","wikidata":"https://www.wikidata.org/wiki/Q5319000","display_name":"Dynamic priority scheduling","level":3,"score":0.14353609085083008},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13931435346603394},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.12622395157814026},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.12012529373168945},{"id":"https://openalex.org/C42407357","wikidata":"https://www.wikidata.org/wiki/Q521","display_name":"Physiology","level":1,"score":0.0},{"id":"https://openalex.org/C119948110","wikidata":"https://www.wikidata.org/wiki/Q7858726","display_name":"Two-level scheduling","level":4,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1278349.1278364","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1278349.1278364","pdf_url":null,"source":{"id":"https://openalex.org/S105046310","display_name":"ACM Transactions on Design Automation of Electronic Systems","issn_l":"1084-4309","issn":["1084-4309","1557-7309"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Design Automation of Electronic Systems","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.108.7805","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.108.7805","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://pllab.cs.nthu.edu.tw/~ypyou/a51-you.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.9100000262260437,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321040","display_name":"National Science Council","ror":"https://ror.org/02kv4zf79"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":32,"referenced_works":["https://openalex.org/W1486780528","https://openalex.org/W1527024979","https://openalex.org/W1558498340","https://openalex.org/W1633471522","https://openalex.org/W1970238527","https://openalex.org/W1979106679","https://openalex.org/W2039097694","https://openalex.org/W2079125893","https://openalex.org/W2095644119","https://openalex.org/W2100963544","https://openalex.org/W2102727118","https://openalex.org/W2103961614","https://openalex.org/W2104726505","https://openalex.org/W2105504170","https://openalex.org/W2110134128","https://openalex.org/W2110615063","https://openalex.org/W2131507936","https://openalex.org/W2135721541","https://openalex.org/W2144306116","https://openalex.org/W2150749964","https://openalex.org/W2155063924","https://openalex.org/W2156348954","https://openalex.org/W2158899676","https://openalex.org/W2163064833","https://openalex.org/W2166243422","https://openalex.org/W2169826970","https://openalex.org/W2171697422","https://openalex.org/W2533651815","https://openalex.org/W2569549435","https://openalex.org/W4249413802","https://openalex.org/W4285719527","https://openalex.org/W4301665104"],"related_works":["https://openalex.org/W2259094912","https://openalex.org/W2371329481","https://openalex.org/W4238764801","https://openalex.org/W4245432303","https://openalex.org/W2017069727","https://openalex.org/W1513380625","https://openalex.org/W2085490248","https://openalex.org/W2123154072","https://openalex.org/W63313507","https://openalex.org/W2152904206"],"abstract_inverted_index":{"Power":[0],"leakage":[1,32,178],"constitutes":[2],"an":[3],"increasing":[4,22,84],"fraction":[5],"of":[6,24,74,86,111,131,172],"the":[7,17,71,83,129,153,170],"total":[8],"power":[9,33,179],"consumption":[10,155],"in":[11,92,168],"modern":[12],"semiconductor":[13],"technologies":[14],"due":[15,81],"to":[16,30,49,64,79,82,107,117,181],"continuing":[18],"size":[19],"reductions":[20],"and":[21,37,52,143,150],"speeds":[23],"transistors.":[25],"Recent":[26],"studies":[27,60],"have":[28],"attempted":[29],"reduce":[31],"using":[34,156],"integrated":[35],"architecture":[36],"compiler":[38,106,141,148],"power-gating":[39,90,112,120,132,173],"mechanisms.":[40],"This":[41],"approach":[42,63],"involves":[43],"compilers":[44],"inserting":[45],"instructions":[46,76,121,133,174],"into":[47,122,146],"programs":[48,80],"shut":[50],"down":[51],"wake":[53],"up":[54],"components,":[55],"as":[56],"appropriate.":[57],"While":[58],"early":[59],"showed":[61],"this":[62,97],"be":[65],"effective,":[66],"there":[67],"are":[68,166],"concerns":[69],"about":[70],"large":[72],"amount":[73,85,130,171],"power-control":[75],"being":[77],"added":[78],"components":[87],"equipped":[88],"with":[89],"controls":[91],"SoC":[93],"design":[94],"platforms.":[95],"In":[96],"article":[98],"we":[99],"present":[100],"a":[101,105,123],"sink-n-hoist":[102],"framework":[103],"for":[104],"generate":[108],"balanced":[109],"scheduling":[110,144],"instructions.":[113],"Our":[114],"solution":[115],"attempts":[116],"merge":[118],"several":[119],"single":[124],"compound":[125],"instruction,":[126],"thereby":[127],"reducing":[128,169,177],"issued.":[134],"We":[135],"performed":[136],"experiments":[137],"by":[138,151],"incorporating":[139],"our":[140,164],"analysis":[142],"policies":[145],"SUIF":[147],"tools":[149],"simulating":[152],"energy":[154],"Wattch":[157],"toolkits.":[158],"The":[159],"experimental":[160],"results":[161],"demonstrate":[162],"that":[163],"mechanisms":[165],"effective":[167],"while":[175],"further":[176],"compared":[180],"previous":[182],"methods.":[183]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":5},{"year":2013,"cited_by_count":2}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
