{"id":"https://openalex.org/W2006261501","doi":"https://doi.org/10.1145/1275571.1275576","title":"A computer architecture education curriculum through the design and implementation of original processors using FPGAs","display_name":"A computer architecture education curriculum through the design and implementation of original processors using FPGAs","publication_year":2004,"publication_date":"2004-01-01","ids":{"openalex":"https://openalex.org/W2006261501","doi":"https://doi.org/10.1145/1275571.1275576","mag":"2006261501"},"language":"en","primary_location":{"id":"doi:10.1145/1275571.1275576","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1275571.1275576","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2004 workshop on Computer architecture education held in conjunction with the 31st International Symposium on Computer Architecture - WCAE '04","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070649314","display_name":"Yutaka Sugawara","orcid":"https://orcid.org/0000-0002-8116-5346"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Yutaka Sugawara","raw_affiliation_strings":["University of Tokyo, Bunkyo-ku, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Bunkyo-ku, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112110720","display_name":"Kei Hiraki","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kei Hiraki","raw_affiliation_strings":["University of Tokyo, Bunkyo-ku, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Bunkyo-ku, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5070649314"],"corresponding_institution_ids":["https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":1.0585,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.7597117,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"3","last_page":"es"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9955000281333923,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9955000281333923,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11283","display_name":"Experimental Learning in Engineering","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/2214","display_name":"Media Technology"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9879000186920166,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.7661911249160767},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7267020344734192},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7018082737922668},{"id":"https://openalex.org/keywords/curriculum","display_name":"Curriculum","score":0.6291998624801636},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.629152238368988},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3648805618286133},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3638700544834137},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.3266916871070862},{"id":"https://openalex.org/keywords/pedagogy","display_name":"Pedagogy","score":0.07403331995010376},{"id":"https://openalex.org/keywords/psychology","display_name":"Psychology","score":0.06246960163116455}],"concepts":[{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.7661911249160767},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7267020344734192},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7018082737922668},{"id":"https://openalex.org/C47177190","wikidata":"https://www.wikidata.org/wiki/Q207137","display_name":"Curriculum","level":2,"score":0.6291998624801636},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.629152238368988},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3648805618286133},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3638700544834137},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.3266916871070862},{"id":"https://openalex.org/C19417346","wikidata":"https://www.wikidata.org/wiki/Q7922","display_name":"Pedagogy","level":1,"score":0.07403331995010376},{"id":"https://openalex.org/C15744967","wikidata":"https://www.wikidata.org/wiki/Q9418","display_name":"Psychology","level":0,"score":0.06246960163116455},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1275571.1275576","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1275571.1275576","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2004 workshop on Computer architecture education held in conjunction with the 31st International Symposium on Computer Architecture - WCAE '04","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.297.4724","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.297.4724","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www4.ncsu.edu/~efg/wcae/2004/submissions/sugawara.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.46000000834465027}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1538592187","https://openalex.org/W1555915743","https://openalex.org/W1699468212","https://openalex.org/W1985156014","https://openalex.org/W2005072728","https://openalex.org/W2065620615","https://openalex.org/W2091923100"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W4200391368","https://openalex.org/W2355315220","https://openalex.org/W2210979487","https://openalex.org/W2074043759","https://openalex.org/W2373535795","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2038503502"],"abstract_inverted_index":{"In":[0,34,54,107],"this":[1,35,108],"paper,":[2,109],"we":[3,110,127],"present":[4],"the":[5,9,13,19,29,51,56,59,63,68,78,92,112,117,121,124,130,134],"new":[6,113],"curriculum":[7,57,114],"of":[8,12,15,21,28,58,80,120,133],"processor":[10],"laboratory":[11,24,60],"Department":[14],"Computer":[16],"Science":[17],"at":[18],"University":[20],"Tokyo.":[22],"This":[23],"is":[25],"a":[26,73,84],"part":[27],"computer":[30],"architecture":[31],"education":[32],"curriculum.":[33],"laboratory,":[36],"students":[37,86],"design":[38,81],"and":[39,49,104,115],"implement":[40,91],"their":[41],"own":[42],"processors":[43,97],"using":[44],"field-programmable":[45],"gate":[46],"arrays":[47],"(FPGAs),":[48],"write":[50],"necessary":[52],"software.":[53],"2003,":[55],"was":[61,70],"changed,":[62],"main":[64],"change":[65],"being":[66],"that":[67],"FPGA":[69,136],"changed":[71],"to":[72,76,90],"large":[74,135],"one":[75],"increase":[77],"range":[79],"trade-offs.":[82],"As":[83],"result,":[85],"have":[87],"been":[88],"enabled":[89],"techniques":[93],"used":[94],"in":[95],"modern":[96],"such":[98],"as":[99],"FPU,":[100],"cache,":[101],"branch":[102],"prediction,":[103],"superscalar":[105],"architecture.":[106],"detail":[111],"note":[116],"educational":[118,131],"results":[119],"year":[122],"following":[123],"changes.":[125],"Especially,":[126],"focus":[128],"on":[129],"advantages":[132],"size.":[137]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2015,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
