{"id":"https://openalex.org/W2121758805","doi":"https://doi.org/10.1145/1250734.1250753","title":"EXOCHI","display_name":"EXOCHI","publication_year":2007,"publication_date":"2007-06-10","ids":{"openalex":"https://openalex.org/W2121758805","doi":"https://doi.org/10.1145/1250734.1250753","mag":"2121758805"},"language":"en","primary_location":{"id":"doi:10.1145/1250734.1250753","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1250734.1250753","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 28th ACM SIGPLAN Conference on Programming Language Design and Implementation","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5008708613","display_name":"Perry H. Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Perry H. Wang","raw_affiliation_strings":["Intel, Santa Clara, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005994838","display_name":"Jamison D. Collins","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jamison D. Collins","raw_affiliation_strings":["Intel, Santa Clara, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019370884","display_name":"Gautham N. Chinya","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gautham N. Chinya","raw_affiliation_strings":["Intel, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054285749","display_name":"Hong Jiang","orcid":"https://orcid.org/0000-0002-1477-9751"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hong Jiang","raw_affiliation_strings":["Intel, Folsom, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Folsom, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101131112","display_name":"Xinmin Tian","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xinmin Tian","raw_affiliation_strings":["Intel, Santa Clara, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009108433","display_name":"Milind Girkar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Milind Girkar","raw_affiliation_strings":["Intel, Santa Clara, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024249953","display_name":"Nick Y. Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nick Y. Yang","raw_affiliation_strings":["Intel, Folsom, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Folsom, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090031333","display_name":"Guei-Yuan Lueh","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Guei-Yuan Lueh","raw_affiliation_strings":["Intel, Santa Clara, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100371015","display_name":"Hong Wang","orcid":"https://orcid.org/0009-0008-2874-2168"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hong Wang","raw_affiliation_strings":["Intel, Santa Clara, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":9,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":15.9222,"has_fulltext":false,"cited_by_count":147,"citation_normalized_percentile":{"value":0.99330592,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"156","last_page":"166"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9929999709129333,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8547389507293701},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.6877256631851196},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.6205888390541077},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6095414161682129},{"id":"https://openalex.org/keywords/multithreading","display_name":"Multithreading","score":0.6023277044296265},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5452005863189697},{"id":"https://openalex.org/keywords/mimd","display_name":"MIMD","score":0.5269623398780823},{"id":"https://openalex.org/keywords/symmetric-multiprocessor-system","display_name":"Symmetric multiprocessor system","score":0.4916136860847473},{"id":"https://openalex.org/keywords/simultaneous-multithreading","display_name":"Simultaneous multithreading","score":0.489034503698349},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3584079146385193}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8547389507293701},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.6877256631851196},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.6205888390541077},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6095414161682129},{"id":"https://openalex.org/C201410400","wikidata":"https://www.wikidata.org/wiki/Q1064412","display_name":"Multithreading","level":3,"score":0.6023277044296265},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5452005863189697},{"id":"https://openalex.org/C21032095","wikidata":"https://www.wikidata.org/wiki/Q1149237","display_name":"MIMD","level":2,"score":0.5269623398780823},{"id":"https://openalex.org/C172430144","wikidata":"https://www.wikidata.org/wiki/Q17111997","display_name":"Symmetric multiprocessor system","level":2,"score":0.4916136860847473},{"id":"https://openalex.org/C85717602","wikidata":"https://www.wikidata.org/wiki/Q82178","display_name":"Simultaneous multithreading","level":4,"score":0.489034503698349},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3584079146385193},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1250734.1250753","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1250734.1250753","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 28th ACM SIGPLAN Conference on Programming Language Design and Implementation","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.800000011920929,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W174757544","https://openalex.org/W1497185130","https://openalex.org/W1566764900","https://openalex.org/W1568192366","https://openalex.org/W2004766113","https://openalex.org/W2032309817","https://openalex.org/W2044788775","https://openalex.org/W2063160743","https://openalex.org/W2086485856","https://openalex.org/W2086794688","https://openalex.org/W2100304243","https://openalex.org/W2108157916","https://openalex.org/W2108792719","https://openalex.org/W2140379632","https://openalex.org/W2144643978","https://openalex.org/W2147943147","https://openalex.org/W2163229756","https://openalex.org/W2168028787","https://openalex.org/W2169706611","https://openalex.org/W4233335396","https://openalex.org/W4236135525","https://openalex.org/W4241388180","https://openalex.org/W4241667468","https://openalex.org/W4285719527","https://openalex.org/W6633932839","https://openalex.org/W6633991270","https://openalex.org/W6672140541"],"related_works":["https://openalex.org/W2118532220","https://openalex.org/W4240807263","https://openalex.org/W2913446311","https://openalex.org/W1532726325","https://openalex.org/W2115561485","https://openalex.org/W2354938433","https://openalex.org/W3142147837","https://openalex.org/W2294358097","https://openalex.org/W2482815832","https://openalex.org/W3142189107"],"abstract_inverted_index":{"Future":[0],"mainstream":[1],"microprocessors":[2],"will":[3],"likely":[4],"integrate":[5],"specialized":[6,37,85],"accelerators,":[7],"such":[8,30],"as":[9],"GPUs,":[10],"onto":[11],"a":[12,25,31,73,124],"single":[13,125],"die":[14],"to":[15,28,64,132,147],"achieve":[16],"better":[17],"performance":[18,149],"and":[19,41,72,92,108,122,150],"power":[20],"efficiency.":[21],"However,":[22],"it":[23],"remains":[24],"keen":[26],"challenge":[27],"program":[29,79],"heterogeneous":[32,66,77,119,145],"multicore":[33],"platform,":[34],"since":[35],"these":[36],"accelerators":[38],"feature":[39],"ISAs":[40],"functionality":[42],"that":[43,82,103],"are":[44],"significantly":[45],"different":[46,133],"from":[47],"the":[48,115,144],"general":[49],"purpose":[50],"CPU":[51,90],"cores.":[52],"In":[53],"this":[54],"paper,":[55],"we":[56],"present":[57],"EXOCHI:":[58],"(1)":[59],"Exoskeleton":[60],"Sequencer(EXO),":[61],"an":[62,98],"architecture":[63,70],"represent":[65],"acceleratorsas":[67],"ISA-based":[68],"MIMD":[69],"resources,":[71],"shared":[74],"virtual":[75],"memory":[76],"multithreaded":[78],"execution":[80],"model":[81],"tightly":[83],"couples":[84],"accelerator":[86],"cores":[87,146],"with":[88,128],"generalpurpose":[89],"cores,":[91],"(2)":[93],"C":[94],"for":[95,118],"Heterogeneous":[96],"Integration(CHI),":[97],"integrated":[99],"C/C++":[100],"programming":[101],"environment":[102],"supports":[104],"accelerator-specific":[105],"inline":[106],"assembly":[107],"domain-specific":[109],"languages.":[110],"The":[111,136],"CHI":[112],"compiler":[113],"extends":[114],"OpenMP":[116],"pragma":[117],"multithreading":[120],"programming,":[121],"produces":[123],"fat":[126],"binary":[127],"code":[129],"sections":[130],"corresponding":[131],"instruction":[134],"sets.":[135],"runtime":[137],"can":[138],"judiciously":[139],"spread":[140],"parallel":[141],"computation":[142],"across":[143],"optimize":[148],"power.":[151]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":7},{"year":2014,"cited_by_count":13},{"year":2013,"cited_by_count":19},{"year":2012,"cited_by_count":23}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2016-06-24T00:00:00"}