{"id":"https://openalex.org/W2162415743","doi":"https://doi.org/10.1145/1248377.1248398","title":"Proximity-aware directory-based coherence for multi-core processor architectures","display_name":"Proximity-aware directory-based coherence for multi-core processor architectures","publication_year":2007,"publication_date":"2007-06-09","ids":{"openalex":"https://openalex.org/W2162415743","doi":"https://doi.org/10.1145/1248377.1248398","mag":"2162415743"},"language":"en","primary_location":{"id":"doi:10.1145/1248377.1248398","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1248377.1248398","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the nineteenth annual ACM symposium on Parallel algorithms and architectures","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060837220","display_name":"Jeffery A. Brown","orcid":null},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California, San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Jeffery A. Brown","raw_affiliation_strings":["University of California, San Diego, La Jolla, CA"],"affiliations":[{"raw_affiliation_string":"University of California, San Diego, La Jolla, CA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067547869","display_name":"Rakesh Kumar","orcid":"https://orcid.org/0000-0002-3290-2629"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rakesh Kumar","raw_affiliation_strings":["University of Illinois at Urbana-Champaign, Urbana, IL"],"affiliations":[{"raw_affiliation_string":"University of Illinois at Urbana-Champaign, Urbana, IL","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065583627","display_name":"Dean M. Tullsen","orcid":"https://orcid.org/0000-0003-3174-9316"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California, San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dean Tullsen","raw_affiliation_strings":["University of California, San Diego, La Jolla, CA"],"affiliations":[{"raw_affiliation_string":"University of California, San Diego, La Jolla, CA","institution_ids":["https://openalex.org/I36258959"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5060837220"],"corresponding_institution_ids":["https://openalex.org/I36258959"],"apc_list":null,"apc_paid":null,"fwci":5.0519,"has_fulltext":false,"cited_by_count":56,"citation_normalized_percentile":{"value":0.95530441,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"126","last_page":"134"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8057535886764526},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7577742338180542},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7176428437232971},{"id":"https://openalex.org/keywords/directory","display_name":"Directory","score":0.6857379674911499},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.6653865575790405},{"id":"https://openalex.org/keywords/coherence","display_name":"Coherence (philosophical gambling strategy)","score":0.6002801060676575},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5997990369796753},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5805018544197083},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.5797777771949768},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.577908992767334},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.530356228351593},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.48453038930892944},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.4569653868675232},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.44089779257774353},{"id":"https://openalex.org/keywords/mesi-protocol","display_name":"MESI protocol","score":0.4261644184589386},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3764552175998688},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.2050587236881256},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.19167762994766235},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.16328537464141846},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.12766039371490479},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.10144972801208496},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.07861563563346863}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8057535886764526},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7577742338180542},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7176428437232971},{"id":"https://openalex.org/C2777683733","wikidata":"https://www.wikidata.org/wiki/Q201456","display_name":"Directory","level":2,"score":0.6857379674911499},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.6653865575790405},{"id":"https://openalex.org/C2781181686","wikidata":"https://www.wikidata.org/wiki/Q4226068","display_name":"Coherence (philosophical gambling strategy)","level":2,"score":0.6002801060676575},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5997990369796753},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5805018544197083},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.5797777771949768},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.577908992767334},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.530356228351593},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.48453038930892944},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.4569653868675232},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.44089779257774353},{"id":"https://openalex.org/C120936851","wikidata":"https://www.wikidata.org/wiki/Q1408065","display_name":"MESI protocol","level":5,"score":0.4261644184589386},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3764552175998688},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.2050587236881256},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.19167762994766235},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.16328537464141846},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12766039371490479},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.10144972801208496},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.07861563563346863},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1248377.1248398","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1248377.1248398","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the nineteenth annual ACM symposium on Parallel algorithms and architectures","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.76.2000","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.76.2000","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www-cse.ucsd.edu/users/tullsen/spaa07.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.44999998807907104,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1970444712","https://openalex.org/W1993254370","https://openalex.org/W2022740893","https://openalex.org/W2036741467","https://openalex.org/W2066632394","https://openalex.org/W2096193215","https://openalex.org/W2100720297","https://openalex.org/W2114421447","https://openalex.org/W2114995630","https://openalex.org/W2127547524","https://openalex.org/W2139239342","https://openalex.org/W2139397536","https://openalex.org/W2141686508","https://openalex.org/W2143515003","https://openalex.org/W2145252892","https://openalex.org/W2154502506","https://openalex.org/W2170537330","https://openalex.org/W2171825402","https://openalex.org/W2243416539","https://openalex.org/W2911669905","https://openalex.org/W4244034697","https://openalex.org/W4251024738","https://openalex.org/W4255387252","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W4285204597","https://openalex.org/W2290195868","https://openalex.org/W3193874149","https://openalex.org/W2139534474","https://openalex.org/W2013212244","https://openalex.org/W2002047509","https://openalex.org/W2352722396","https://openalex.org/W2107914397","https://openalex.org/W3026856133","https://openalex.org/W13351917"],"abstract_inverted_index":{"As":[0],"the":[1,23,61],"number":[2],"of":[3],"cores":[4],"increases":[5],"on":[6],"chip":[7,66],"multiprocessors,":[8],"coherence":[9,40],"is":[10,20],"fast":[11],"becoming":[12],"a":[13,42,52],"central":[14],"issue":[15],"for":[16,41],"multi-core":[17,43],"performance.":[18],"This":[19,34],"exacerbated":[21],"by":[22],"fact":[24],"that":[25,45],"interconnection":[26],"speeds":[27],"are":[28],"not":[29],"scaling":[30],"well":[31],"with":[32],"technology.":[33],"paper":[35],"describes":[36],"mechanisms":[37],"to":[38],"accelerate":[39],"architecture":[44],"has":[46],"multiple":[47],"private":[48],"L2":[49],"caches":[50],"and":[51,68],"scalable":[53],"point-to-point":[54],"interconnect":[55],"between":[56,65],"cores.":[57],"These":[58],"techniques":[59],"exploit":[60],"differences":[62],"in":[63],"geometry":[64],"multiprocessors":[67],"traditional":[69],"multiprocessor":[70],"architectures.":[71]},"counts_by_year":[{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":9},{"year":2012,"cited_by_count":9}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
