{"id":"https://openalex.org/W2036781853","doi":"https://doi.org/10.1145/1244002.1244159","title":"Fast, accurate design space exploration of embedded systems memory configurations","display_name":"Fast, accurate design space exploration of embedded systems memory configurations","publication_year":2007,"publication_date":"2007-03-11","ids":{"openalex":"https://openalex.org/W2036781853","doi":"https://doi.org/10.1145/1244002.1244159","mag":"2036781853"},"language":"en","primary_location":{"id":"doi:10.1145/1244002.1244159","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1244002.1244159","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2007 ACM symposium on Applied computing","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5086514103","display_name":"Jason D. Hiser","orcid":null},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Jason D. Hiser","raw_affiliation_strings":["University of Virginia, Charlottesville, VA"],"affiliations":[{"raw_affiliation_string":"University of Virginia, Charlottesville, VA","institution_ids":["https://openalex.org/I51556381"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068264173","display_name":"Jack W. Davidson","orcid":null},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jack W. Davidson","raw_affiliation_strings":["University of Virginia, Charlottesville, VA"],"affiliations":[{"raw_affiliation_string":"University of Virginia, Charlottesville, VA","institution_ids":["https://openalex.org/I51556381"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108249713","display_name":"David Whalley","orcid":null},"institutions":[{"id":"https://openalex.org/I103163165","display_name":"Florida State University","ror":"https://ror.org/05g3dte14","country_code":"US","type":"education","lineage":["https://openalex.org/I103163165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David B. Whalley","raw_affiliation_strings":["Flordia State University, Tallahasse, FL","Flordia State University, Tallahasse, FL#TAB#"],"affiliations":[{"raw_affiliation_string":"Flordia State University, Tallahasse, FL","institution_ids":["https://openalex.org/I103163165"]},{"raw_affiliation_string":"Flordia State University, Tallahasse, FL#TAB#","institution_ids":["https://openalex.org/I103163165"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5086514103"],"corresponding_institution_ids":["https://openalex.org/I51556381"],"apc_list":null,"apc_paid":null,"fwci":0.6365,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.70844895,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"699","last_page":"706"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7662481665611267},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.6340922713279724},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.5840151906013489},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.5044916868209839},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.4945625960826874},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.48348838090896606},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.41582635045051575},{"id":"https://openalex.org/keywords/extended-memory","display_name":"Extended memory","score":0.41371679306030273},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.4005975127220154},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.32058340311050415},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2947673797607422},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.28314605355262756},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2718995213508606},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.1440521478652954}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7662481665611267},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.6340922713279724},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.5840151906013489},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.5044916868209839},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.4945625960826874},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.48348838090896606},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.41582635045051575},{"id":"https://openalex.org/C171675096","wikidata":"https://www.wikidata.org/wiki/Q1143380","display_name":"Extended memory","level":4,"score":0.41371679306030273},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.4005975127220154},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.32058340311050415},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2947673797607422},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.28314605355262756},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2718995213508606},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.1440521478652954}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1244002.1244159","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1244002.1244159","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2007 ACM symposium on Applied computing","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.73.232","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.73.232","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cs.fsu.edu/~whalley/papers/sac07.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8500000238418579,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1569032152","https://openalex.org/W1686420892","https://openalex.org/W1967022475","https://openalex.org/W1969288309","https://openalex.org/W1975323530","https://openalex.org/W1985515302","https://openalex.org/W1992763756","https://openalex.org/W1993988399","https://openalex.org/W2032297914","https://openalex.org/W2034928524","https://openalex.org/W2075183718","https://openalex.org/W2091890752","https://openalex.org/W2096615830","https://openalex.org/W2097211482","https://openalex.org/W2102727118","https://openalex.org/W2104816779","https://openalex.org/W2105560756","https://openalex.org/W2112348674","https://openalex.org/W2122418911","https://openalex.org/W2158737060","https://openalex.org/W2163270257","https://openalex.org/W2170990025","https://openalex.org/W4238321249"],"related_works":["https://openalex.org/W2334181344","https://openalex.org/W2558276258","https://openalex.org/W2401095501","https://openalex.org/W2362277122","https://openalex.org/W2295799647","https://openalex.org/W4293054943","https://openalex.org/W1531461453","https://openalex.org/W4243333834","https://openalex.org/W4249130715","https://openalex.org/W2753615087"],"abstract_inverted_index":{"The":[0,95],"memory":[1,15,39,49,87,93,164],"hierarchy":[2,16,50],"is":[3,97,108],"often":[4],"a":[5,78,90,104],"critical":[6],"component":[7],"of":[8,29,45,56,66,92,100,115,123,131,139,162],"an":[9,84],"embedded":[10,13,150],"system.":[11,31],"An":[12],"system's":[14,174],"can":[17],"have":[18],"dramatic":[19],"impact":[20],"on":[21,89],"the":[22,30,43,48,67,116,124,140,149,153,159,168,173],"overall":[23],"cost,":[24],"performance,":[25],"and":[26,54,166],"power":[27],"consumption":[28],"Consequently,":[32],"designers":[33],"spend":[34],"considerable":[35],"time":[36],"evaluating":[37],"potential":[38,163],"system":[40,151],"designs.":[41],"Unfortunately,":[42],"range":[44],"options":[46],"in":[47],"(e.g.,":[51],"number,":[52],"size,":[53],"type":[55],"caches,":[57],"on-chip":[58],"SRAM,":[59],"DRAM,":[60],"EPROM,":[61],"etc.)":[62],"makes":[63],"thorough":[64],"exploration":[65],"design":[68,160,175],"space":[69,161],"using":[70],"typical":[71],"simulation":[72],"techniques":[73],"infeasible.":[74],"This":[75,144],"paper":[76],"describes":[77],"fast,":[79,145],"accurate":[80,146],"technique":[81,96,147],"to":[82,155],"estimate":[83],"application's":[85],"average":[86],"latency":[88],"set":[91],"hierarchies.":[94],"fast---two":[98],"orders":[99],"magnitude":[101],"faster":[102],"than":[103],"full":[105],"simulation.":[106],"It":[107],"also":[109],"accurate---extensive":[110],"measurements":[111],"show":[112],"that":[113,170],"70%":[114],"estimates":[117,133],"were":[118,134],"within":[119,135],"1":[120],"percentage":[121,137],"point":[122],"actual":[125,141],"cycle":[126,142],"count":[127],"while":[128],"over":[129],"99%":[130],"all":[132],"10":[136],"points":[138],"count.":[143],"provides":[148],"designer":[152],"ability":[154],"more":[156],"fully":[157],"explore":[158],"hierarchies":[165],"select":[167],"one":[169],"best":[171],"meets":[172],"requirements.":[176]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}