{"id":"https://openalex.org/W2017706622","doi":"https://doi.org/10.1145/1241601.1241611","title":"A hardware/software framework for supporting transactional memory in a MPSoC environment","display_name":"A hardware/software framework for supporting transactional memory in a MPSoC environment","publication_year":2007,"publication_date":"2007-03-01","ids":{"openalex":"https://openalex.org/W2017706622","doi":"https://doi.org/10.1145/1241601.1241611","mag":"2017706622"},"language":"en","primary_location":{"id":"doi:10.1145/1241601.1241611","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1241601.1241611","pdf_url":null,"source":{"id":"https://openalex.org/S4210193905","display_name":"ACM SIGARCH Computer Architecture News","issn_l":"0163-5964","issn":["0163-5964","1943-5851"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320740","host_organization_name":"ACM SIGARCH","host_organization_lineage":["https://openalex.org/P4310320740"],"host_organization_lineage_names":["ACM SIGARCH"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM SIGARCH Computer Architecture News","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021455020","display_name":"Cesare Ferri","orcid":null},"institutions":[{"id":"https://openalex.org/I27804330","display_name":"Brown University","ror":"https://ror.org/05gq02987","country_code":"US","type":"education","lineage":["https://openalex.org/I27804330"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Cesare Ferri","raw_affiliation_strings":["Brown University, Providence, RI","Brown University, Providence, RI,"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Brown University, Providence, RI","institution_ids":["https://openalex.org/I27804330"]},{"raw_affiliation_string":"Brown University, Providence, RI,","institution_ids":["https://openalex.org/I27804330"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007533105","display_name":"Tali Moreshet","orcid":"https://orcid.org/0000-0002-1177-5245"},"institutions":[{"id":"https://openalex.org/I118020396","display_name":"Swarthmore College","ror":"https://ror.org/012dg8a96","country_code":"US","type":"education","lineage":["https://openalex.org/I118020396"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tali Moreshet","raw_affiliation_strings":["Swarthmore College, Swarthmore, PA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Swarthmore College, Swarthmore, PA","institution_ids":["https://openalex.org/I118020396"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047635410","display_name":"R. Iris Bahar","orcid":"https://orcid.org/0000-0001-6927-8527"},"institutions":[{"id":"https://openalex.org/I27804330","display_name":"Brown University","ror":"https://ror.org/05gq02987","country_code":"US","type":"education","lineage":["https://openalex.org/I27804330"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Iris Bahar","raw_affiliation_strings":["Brown University, Providence, RI","Brown University, Providence, RI,"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Brown University, Providence, RI","institution_ids":["https://openalex.org/I27804330"]},{"raw_affiliation_string":"Brown University, Providence, RI,","institution_ids":["https://openalex.org/I27804330"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043408422","display_name":"Luca Benini","orcid":"https://orcid.org/0000-0001-8068-3806"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Benini","raw_affiliation_strings":["University of Bologna, Bologna, Italy","University of Bologna , Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]},{"raw_affiliation_string":"University of Bologna , Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5086347882","display_name":"Maurice Herlihy","orcid":"https://orcid.org/0000-0002-3059-8926"},"institutions":[{"id":"https://openalex.org/I27804330","display_name":"Brown University","ror":"https://ror.org/05gq02987","country_code":"US","type":"education","lineage":["https://openalex.org/I27804330"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Maurice Herlihy","raw_affiliation_strings":["Brown University, Providence, RI","Brown University, Providence, RI,"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Brown University, Providence, RI","institution_ids":["https://openalex.org/I27804330"]},{"raw_affiliation_string":"Brown University, Providence, RI,","institution_ids":["https://openalex.org/I27804330"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.6591,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.90311087,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"35","issue":"1","first_page":"47","last_page":"54"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/transactional-memory","display_name":"Transactional memory","score":0.9518800973892212},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.833967924118042},{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.7465533018112183},{"id":"https://openalex.org/keywords/software-transactional-memory","display_name":"Software transactional memory","score":0.733844518661499},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6529743671417236},{"id":"https://openalex.org/keywords/concurrency","display_name":"Concurrency","score":0.6128082871437073},{"id":"https://openalex.org/keywords/lock","display_name":"Lock (firearm)","score":0.5565589070320129},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.5145001411437988},{"id":"https://openalex.org/keywords/optimistic-concurrency-control","display_name":"Optimistic concurrency control","score":0.4315968155860901},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.4126124382019043},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4120086133480072},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.36110246181488037},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.35203295946121216},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3254232108592987},{"id":"https://openalex.org/keywords/concurrency-control","display_name":"Concurrency control","score":0.2693248689174652},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.10038489103317261}],"concepts":[{"id":"https://openalex.org/C134277064","wikidata":"https://www.wikidata.org/wiki/Q878206","display_name":"Transactional memory","level":3,"score":0.9518800973892212},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.833967924118042},{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.7465533018112183},{"id":"https://openalex.org/C167149655","wikidata":"https://www.wikidata.org/wiki/Q1189004","display_name":"Software transactional memory","level":4,"score":0.733844518661499},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6529743671417236},{"id":"https://openalex.org/C193702766","wikidata":"https://www.wikidata.org/wiki/Q1414548","display_name":"Concurrency","level":2,"score":0.6128082871437073},{"id":"https://openalex.org/C174839445","wikidata":"https://www.wikidata.org/wiki/Q1134386","display_name":"Lock (firearm)","level":2,"score":0.5565589070320129},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.5145001411437988},{"id":"https://openalex.org/C79240183","wikidata":"https://www.wikidata.org/wiki/Q1779327","display_name":"Optimistic concurrency control","level":5,"score":0.4315968155860901},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.4126124382019043},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4120086133480072},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.36110246181488037},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.35203295946121216},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3254232108592987},{"id":"https://openalex.org/C84511453","wikidata":"https://www.wikidata.org/wiki/Q2914952","display_name":"Concurrency control","level":3,"score":0.2693248689174652},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.10038489103317261},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C208087996","wikidata":"https://www.wikidata.org/wiki/Q5283142","display_name":"Distributed concurrency control","level":4,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C75949130","wikidata":"https://www.wikidata.org/wiki/Q848010","display_name":"Database transaction","level":2,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/1241601.1241611","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1241601.1241611","pdf_url":null,"source":{"id":"https://openalex.org/S4210193905","display_name":"ACM SIGARCH Computer Architecture News","issn_l":"0163-5964","issn":["0163-5964","1943-5851"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320740","host_organization_name":"ACM SIGARCH","host_organization_lineage":["https://openalex.org/P4310320740"],"host_organization_lineage_names":["ACM SIGARCH"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM SIGARCH Computer Architecture News","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.214.8852","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.214.8852","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.swarthmore.edu/NatSci/tali/publications/ferri_CompArchNews.pdf","raw_type":"text"},{"id":"pmh:oai:cris.unibo.it:11585/50024","is_oa":false,"landing_page_url":"http://hdl.handle.net/11585/50024","pdf_url":null,"source":{"id":"https://openalex.org/S4306402579","display_name":"Archivio istituzionale della ricerca (Alma Mater Studiorum Universit\u00e0 di Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210117483","host_organization_name":"Istituto di Ematologia di Bologna","host_organization_lineage":["https://openalex.org/I4210117483"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8799999952316284,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W73121609","https://openalex.org/W1580087508","https://openalex.org/W1959561997","https://openalex.org/W2013021588","https://openalex.org/W2032204694","https://openalex.org/W2099537990","https://openalex.org/W2105055683","https://openalex.org/W2105772643","https://openalex.org/W2107150212","https://openalex.org/W2108204150","https://openalex.org/W2111919017","https://openalex.org/W2113751407","https://openalex.org/W2114100940","https://openalex.org/W2129990308","https://openalex.org/W2135047781","https://openalex.org/W2141094479","https://openalex.org/W2149473197","https://openalex.org/W2149590159","https://openalex.org/W2151290553","https://openalex.org/W2160642395","https://openalex.org/W2162351670","https://openalex.org/W2164095419","https://openalex.org/W2169666835","https://openalex.org/W2769656678","https://openalex.org/W4234703016","https://openalex.org/W4242949098","https://openalex.org/W6674041293"],"related_works":["https://openalex.org/W1545706510","https://openalex.org/W2105254463","https://openalex.org/W2040281750","https://openalex.org/W1505691835","https://openalex.org/W3171202327","https://openalex.org/W4298036533","https://openalex.org/W3083604022","https://openalex.org/W2963879329","https://openalex.org/W2017706622","https://openalex.org/W1777082217"],"abstract_inverted_index":{"Manufacturers":[0],"are":[1],"focusing":[2],"on":[3],"multiprocessor-system-on-a-chip":[4],"(MPSoC)":[5],"architectures":[6],"in":[7,69,83],"order":[8],"to":[9,31,66,96,128],"provide":[10],"increased":[11,15],"concurrency,":[12],"rather":[13],"than":[14],"clock":[16],"speed,":[17],"for":[18,116,138,167],"both":[19],"large-scale":[20],"as":[21,23,63],"well":[22],"embedded":[24,97,118,169],"systems.":[25,71],"Traditionally":[26],"lock-based":[27,52,67],"synchronization":[28,53,68],"is":[29,162],"provided":[30],"support":[32],"concurrency;":[33],"however,":[34],"managing":[35],"locks":[36,82],"can":[37,54],"be":[38,55],"very":[39],"difficult":[40],"and":[41,48,90,135,154,157],"error":[42],"prone.":[43],"In":[44,105],"addition,":[45],"the":[46,139],"performance":[47,89,136],"power":[49,134],"cost":[50],"of":[51,85,87,122,151],"high.":[56],"Transactional":[57],"memories":[58],"have":[59],"been":[60,74,102],"extensively":[61],"investigated":[62],"an":[64,117],"alternative":[65],"general-purpose":[70],"It":[72],"has":[73,79,100],"shown":[75],"that":[76,159],"transactional":[77,113,140,160],"memory":[78,114,141,161],"advantages":[80],"over":[81,148],"terms":[84],"ease":[86],"programming,":[88],"energy":[91],"consumption.":[92],"However,":[93],"their":[94],"applicability":[95],"multi-core":[98,119],"platforms":[99],"not":[101],"explored":[103],"yet.":[104],"this":[106],"paper,":[107],"we":[108,143],"demonstrate":[109],"a":[110,123,149,163],"complete":[111],"hardware":[112],"solution":[115],"architecture,":[120],"consisting":[121],"cache-coherent":[124],"ARM-based":[125],"cluster,":[126],"similar":[127],"ARM's":[129],"MPCore.":[130],"Using":[131],"cycle":[132],"accurate":[133],"models":[137],"hardware,":[142],"evaluate":[144],"our":[145],"architectural":[146],"framework":[147],"set":[150],"different":[152],"system":[153],"application":[155],"settings,":[156],"show":[158],"promising":[164],"solution,":[165],"even":[166],"resource-constrained":[168],"multiprocessors.":[170]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":2}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}