{"id":"https://openalex.org/W2116059830","doi":"https://doi.org/10.1145/123186.123234","title":"A new min-cut placement algorithm for timing assurance layout design meeting net length constraint","display_name":"A new min-cut placement algorithm for timing assurance layout design meeting net length constraint","publication_year":1990,"publication_date":"1990-01-01","ids":{"openalex":"https://openalex.org/W2116059830","doi":"https://doi.org/10.1145/123186.123234","mag":"2116059830"},"language":"en","primary_location":{"id":"doi:10.1145/123186.123234","is_oa":true,"landing_page_url":"https://doi.org/10.1145/123186.123234","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/123186.123234","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Conference proceedings on 27th ACM/IEEE design automation conference  - DAC '90","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://dl.acm.org/doi/pdf/10.1145/123186.123234","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109328442","display_name":"Masayuki Terai","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masayuki Terai","raw_affiliation_strings":["ASIC Design Engineering Center, Mitsubishi Electric Corporation, Itami, Hyogo 664, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ASIC Design Engineering Center, Mitsubishi Electric Corporation, Itami, Hyogo 664, Japan","institution_ids":["https://openalex.org/I4210133125"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035481948","display_name":"Kazuhiro Takahashi","orcid":"https://orcid.org/0000-0002-9358-0117"},"institutions":[{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kazuhiro Takahashi","raw_affiliation_strings":["ASIC Design Engineering Center, Mitsubishi Electric Corporation, Itami, Hyogo 664, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ASIC Design Engineering Center, Mitsubishi Electric Corporation, Itami, Hyogo 664, Japan","institution_ids":["https://openalex.org/I4210133125"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5105781219","display_name":"Koji Sato","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Koji Sato","raw_affiliation_strings":["ASIC Design Engineering Center, Mitsubishi Electric Corporation, Itami, Hyogo 664, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ASIC Design Engineering Center, Mitsubishi Electric Corporation, Itami, Hyogo 664, Japan","institution_ids":["https://openalex.org/I4210133125"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6561,"has_fulltext":true,"cited_by_count":27,"citation_normalized_percentile":{"value":0.73929664,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"96","last_page":"102"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.6458160877227783},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6398432850837708},{"id":"https://openalex.org/keywords/net","display_name":"Net (polyhedron)","score":0.5972769260406494},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.5828149914741516},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.5456238389015198},{"id":"https://openalex.org/keywords/algorithm-design","display_name":"Algorithm design","score":0.48056986927986145},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.4761074483394623},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.446074515581131},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.44315701723098755},{"id":"https://openalex.org/keywords/page-layout","display_name":"Page layout","score":0.4385170340538025},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23828959465026855},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.1541065275669098},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1388651430606842},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09072238206863403},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.08096113801002502}],"concepts":[{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.6458160877227783},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6398432850837708},{"id":"https://openalex.org/C14166107","wikidata":"https://www.wikidata.org/wiki/Q253829","display_name":"Net (polyhedron)","level":2,"score":0.5972769260406494},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.5828149914741516},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.5456238389015198},{"id":"https://openalex.org/C106516650","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm design","level":2,"score":0.48056986927986145},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.4761074483394623},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.446074515581131},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.44315701723098755},{"id":"https://openalex.org/C188985296","wikidata":"https://www.wikidata.org/wiki/Q868954","display_name":"Page layout","level":2,"score":0.4385170340538025},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23828959465026855},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.1541065275669098},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1388651430606842},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09072238206863403},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.08096113801002502},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.0},{"id":"https://openalex.org/C112698675","wikidata":"https://www.wikidata.org/wiki/Q37038","display_name":"Advertising","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/123186.123234","is_oa":true,"landing_page_url":"https://doi.org/10.1145/123186.123234","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/123186.123234","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Conference proceedings on 27th ACM/IEEE design automation conference  - DAC '90","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/123186.123234","is_oa":true,"landing_page_url":"https://doi.org/10.1145/123186.123234","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/123186.123234","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Conference proceedings on 27th ACM/IEEE design automation conference  - DAC '90","raw_type":"proceedings-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2116059830.pdf","grobid_xml":"https://content.openalex.org/works/W2116059830.grobid-xml"},"referenced_works_count":8,"referenced_works":["https://openalex.org/W2030852227","https://openalex.org/W2076243583","https://openalex.org/W2099397574","https://openalex.org/W2103499632","https://openalex.org/W2123094965","https://openalex.org/W2139071021","https://openalex.org/W2149949638","https://openalex.org/W3217150240"],"related_works":["https://openalex.org/W4232019485","https://openalex.org/W2028052815","https://openalex.org/W2076413498","https://openalex.org/W2164834710","https://openalex.org/W4327499872","https://openalex.org/W2123512677","https://openalex.org/W2116259070","https://openalex.org/W2128528443","https://openalex.org/W2097706495","https://openalex.org/W2066822161"],"abstract_inverted_index":{"This":[0,34],"paper":[1],"presents":[2],"a":[3],"new":[4],"min-cut":[5],"placement":[6],"algorithm":[7,23,35],"for":[8,42],"timing":[9],"assurance":[10],"layout":[11,40],"design.":[12],"When":[13],"critical":[14],"nets":[15],"are":[16],"given":[17],"net":[18],"length":[19],"constraints,":[20],"the":[21,29,39],"proposed":[22],"can":[24],"place":[25],"cells":[26],"so":[27],"that":[28],"constraints":[30],"may":[31],"be":[32],"met.":[33],"is":[36],"built":[37],"into":[38],"system":[41],"gate":[43,61],"arrays":[44],"called":[45],"GALOP":[46],"[1]":[47],"and":[48],"has":[49],"been":[50],"successfully":[51],"applied":[52],"to":[53],"clock":[54],"skew":[55],"control":[56],"of":[57],"an":[58],"ECL":[59],"12K-gate":[60],"array.":[62]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}