{"id":"https://openalex.org/W2061320983","doi":"https://doi.org/10.1145/1229428.1229451","title":"Latency hiding through multithreading on a network processor","display_name":"Latency hiding through multithreading on a network processor","publication_year":2007,"publication_date":"2007-03-14","ids":{"openalex":"https://openalex.org/W2061320983","doi":"https://doi.org/10.1145/1229428.1229451","mag":"2061320983"},"language":"en","primary_location":{"id":"doi:10.1145/1229428.1229451","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1229428.1229451","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070940269","display_name":"Xiaofeng Guo","orcid":"https://orcid.org/0000-0001-5306-1219"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiaofeng Guo","raw_affiliation_strings":["Intel Asia-Pacific Research &amp; Development Ltd., Shanghai, China","Intel Asia-Pacific Research & Development Ltd., Shanghai, China#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Asia-Pacific Research &amp; Development Ltd., Shanghai, China","institution_ids":[]},{"raw_affiliation_string":"Intel Asia-Pacific Research & Development Ltd., Shanghai, China#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100909399","display_name":"Jinquan Dai","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jinquan Dai","raw_affiliation_strings":["Intel Asia-Pacific Research &amp; Development Ltd., Shanghai, China","Intel Asia-Pacific Research & Development Ltd., Shanghai, China#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Asia-Pacific Research &amp; Development Ltd., Shanghai, China","institution_ids":[]},{"raw_affiliation_string":"Intel Asia-Pacific Research & Development Ltd., Shanghai, China#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100408780","display_name":"Long Li","orcid":"https://orcid.org/0000-0002-7693-9722"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Long Li","raw_affiliation_strings":["Intel Asia-Pacific Research &amp; Development Ltd., Shanghai, China","Intel Asia-Pacific Research & Development Ltd., Shanghai, China#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Asia-Pacific Research &amp; Development Ltd., Shanghai, China","institution_ids":[]},{"raw_affiliation_string":"Intel Asia-Pacific Research & Development Ltd., Shanghai, China#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042330595","display_name":"Zhiyuan Lv","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhiyuan Lv","raw_affiliation_strings":["Intel Asia-Pacific Research &amp; Development Ltd., Shanghai, China","Intel Asia-Pacific Research & Development Ltd., Shanghai, China#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Asia-Pacific Research &amp; Development Ltd., Shanghai, China","institution_ids":[]},{"raw_affiliation_string":"Intel Asia-Pacific Research & Development Ltd., Shanghai, China#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002921558","display_name":"Prashant Chandra","orcid":"https://orcid.org/0000-0001-8864-1707"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Prashant R. Chandra","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA","Intel Corporation, Santa Clara, CA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"130","last_page":"131"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11241","display_name":"Advanced Malware Detection Techniques","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multithreading","display_name":"Multithreading","score":0.9052290916442871},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7694793939590454},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.757121205329895},{"id":"https://openalex.org/keywords/simultaneous-multithreading","display_name":"Simultaneous multithreading","score":0.6300000548362732},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.37311264872550964},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33617377281188965},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.315520316362381},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.259944349527359},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.14444079995155334}],"concepts":[{"id":"https://openalex.org/C201410400","wikidata":"https://www.wikidata.org/wiki/Q1064412","display_name":"Multithreading","level":3,"score":0.9052290916442871},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7694793939590454},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.757121205329895},{"id":"https://openalex.org/C85717602","wikidata":"https://www.wikidata.org/wiki/Q82178","display_name":"Simultaneous multithreading","level":4,"score":0.6300000548362732},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.37311264872550964},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33617377281188965},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.315520316362381},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.259944349527359},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.14444079995155334}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1229428.1229451","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1229428.1229451","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2024333047","https://openalex.org/W2089467613","https://openalex.org/W4235011932"],"related_works":["https://openalex.org/W2118532220","https://openalex.org/W4240807263","https://openalex.org/W2913446311","https://openalex.org/W1532726325","https://openalex.org/W2354938433","https://openalex.org/W3142147837","https://openalex.org/W2115561485","https://openalex.org/W1987511199","https://openalex.org/W35114839","https://openalex.org/W4248655967"],"abstract_inverted_index":{"No":[0],"abstract":[1],"available.":[2]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
