{"id":"https://openalex.org/W2115897253","doi":"https://doi.org/10.1145/1228784.1228858","title":"Using standard asic back-end for qdi asynchronous circuits","display_name":"Using standard asic back-end for qdi asynchronous circuits","publication_year":2007,"publication_date":"2007-03-11","ids":{"openalex":"https://openalex.org/W2115897253","doi":"https://doi.org/10.1145/1228784.1228858","mag":"2115897253"},"language":"en","primary_location":{"id":"doi:10.1145/1228784.1228858","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1228784.1228858","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069865058","display_name":"Mehrdad Najibi","orcid":null},"institutions":[{"id":"https://openalex.org/I158248296","display_name":"Amirkabir University of Technology","ror":"https://ror.org/04gzbav43","country_code":"IR","type":"education","lineage":["https://openalex.org/I158248296"]}],"countries":["IR"],"is_corresponding":true,"raw_author_name":"Mehrdad Najibi","raw_affiliation_strings":["Amirkabir University of Technology, Tehran, Iran","Amirkabir University of Technology, Tehran, IRAN"],"affiliations":[{"raw_affiliation_string":"Amirkabir University of Technology, Tehran, Iran","institution_ids":["https://openalex.org/I158248296"]},{"raw_affiliation_string":"Amirkabir University of Technology, Tehran, IRAN","institution_ids":["https://openalex.org/I158248296"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010366170","display_name":"Kamran Saleh","orcid":null},"institutions":[{"id":"https://openalex.org/I158248296","display_name":"Amirkabir University of Technology","ror":"https://ror.org/04gzbav43","country_code":"IR","type":"education","lineage":["https://openalex.org/I158248296"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Kamran Saleh","raw_affiliation_strings":["Amirkabir University of Technology, Tehran, Iran","Amirkabir University of Technology, Tehran, IRAN"],"affiliations":[{"raw_affiliation_string":"Amirkabir University of Technology, Tehran, Iran","institution_ids":["https://openalex.org/I158248296"]},{"raw_affiliation_string":"Amirkabir University of Technology, Tehran, IRAN","institution_ids":["https://openalex.org/I158248296"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5085021768","display_name":"Hossein Pedram","orcid":"https://orcid.org/0000-0002-2331-0568"},"institutions":[{"id":"https://openalex.org/I158248296","display_name":"Amirkabir University of Technology","ror":"https://ror.org/04gzbav43","country_code":"IR","type":"education","lineage":["https://openalex.org/I158248296"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Hossein Pedram","raw_affiliation_strings":["Amirkabir University of Technology, Tehran, Iran","Amirkabir University of Technology, Tehran, IRAN"],"affiliations":[{"raw_affiliation_string":"Amirkabir University of Technology, Tehran, Iran","institution_ids":["https://openalex.org/I158248296"]},{"raw_affiliation_string":"Amirkabir University of Technology, Tehran, IRAN","institution_ids":["https://openalex.org/I158248296"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5069865058"],"corresponding_institution_ids":["https://openalex.org/I158248296"],"apc_list":null,"apc_paid":null,"fwci":2.1075,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.8760525,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"299","last_page":"304"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7619924545288086},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.6979005336761475},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.6778277158737183},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.5547894239425659},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5147676467895508},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4734444320201874},{"id":"https://openalex.org/keywords/limiting","display_name":"Limiting","score":0.46718624234199524},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.39606088399887085},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34239715337753296},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2899462580680847},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1221335232257843},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08052486181259155},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.07176670432090759}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7619924545288086},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.6979005336761475},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.6778277158737183},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.5547894239425659},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5147676467895508},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4734444320201874},{"id":"https://openalex.org/C188198153","wikidata":"https://www.wikidata.org/wiki/Q1613840","display_name":"Limiting","level":2,"score":0.46718624234199524},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.39606088399887085},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34239715337753296},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2899462580680847},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1221335232257843},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08052486181259155},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.07176670432090759},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1228784.1228858","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1228784.1228858","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.550000011920929,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W16511050","https://openalex.org/W336063547","https://openalex.org/W2029005287","https://openalex.org/W2108432348","https://openalex.org/W2108454771","https://openalex.org/W2132492038","https://openalex.org/W2150872535","https://openalex.org/W2487142227"],"related_works":["https://openalex.org/W4288055011","https://openalex.org/W2100360214","https://openalex.org/W4242912623","https://openalex.org/W2993028905","https://openalex.org/W2110396545","https://openalex.org/W2366772698","https://openalex.org/W2012158213","https://openalex.org/W2100157586","https://openalex.org/W2142651762","https://openalex.org/W2140565566"],"abstract_inverted_index":{"Asynchronous":[0],"circuits":[1,30,39,59],"already":[2],"have":[3],"shown":[4],"their":[5],"benefits.":[6],"The":[7,88],"main":[8,80],"drawback":[9],"is":[10,66,78,101],"the":[11,21,25,55,79,84,102,106],"lack":[12],"of":[13,24,37,54,104,108],"powerful":[14,35],"CAD":[15,110],"and":[16,42,70],"layout":[17,62,86],"generation":[18,63],"tools":[19],"limiting":[20,83],"widespread":[22],"use":[23,107],"asynchronous":[26,29,38],"methodology.":[27],"QDI":[28,58],"are":[31],"known":[32],"as":[33],"a":[34],"category":[36],"targeting":[40],"performance":[41],"power":[43],"driven":[44],"design.":[45],"In":[46],"this":[47],"paper":[48],"we":[49],"addressed":[50],"standard":[51,61,85,109],"cell":[52,73],"implementation":[53],"template":[56],"based":[57],"utilizing":[60],"tools.":[64,111],"This":[65],"achieved":[67],"by":[68],"analyzing":[69],"removing":[71],"outer":[72],"isochronic":[74,89],"fork":[75,90],"constraint":[76],"which":[77,100],"timing":[81],"constraints":[82],"generation.":[87],"free":[91],"final":[92],"netlist":[93],"has":[94],"10--20%":[95],"area":[96],"overhead":[97],"in":[98],"average":[99],"cost":[103],"facilitating":[105]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
