{"id":"https://openalex.org/W2132337134","doi":"https://doi.org/10.1145/1228784.1228833","title":"Novel architectures for efficient (m, n) parallel counters","display_name":"Novel architectures for efficient (m, n) parallel counters","publication_year":2007,"publication_date":"2007-03-11","ids":{"openalex":"https://openalex.org/W2132337134","doi":"https://doi.org/10.1145/1228784.1228833","mag":"2132337134"},"language":"en","primary_location":{"id":"doi:10.1145/1228784.1228833","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1228784.1228833","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5057539175","display_name":"Sreehari Veeramachaneni","orcid":"https://orcid.org/0000-0001-7744-4580"},"institutions":[{"id":"https://openalex.org/I64189192","display_name":"International Institute of Information Technology, Hyderabad","ror":"https://ror.org/05f11g639","country_code":"IN","type":"education","lineage":["https://openalex.org/I64189192"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sreehari Veeramachaneni","raw_affiliation_strings":["Center for VLSI and Embedded System Technologies, Hyderabad, India","Center for VLSI and Embedded System Technologies, Hyderabad, India#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Center for VLSI and Embedded System Technologies, Hyderabad, India","institution_ids":["https://openalex.org/I64189192"]},{"raw_affiliation_string":"Center for VLSI and Embedded System Technologies, Hyderabad, India#TAB#","institution_ids":["https://openalex.org/I64189192"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064286485","display_name":"Avinash Lingamneni","orcid":null},"institutions":[{"id":"https://openalex.org/I64189192","display_name":"International Institute of Information Technology, Hyderabad","ror":"https://ror.org/05f11g639","country_code":"IN","type":"education","lineage":["https://openalex.org/I64189192"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Avinash Lingamneni","raw_affiliation_strings":["Center for VLSI and Embedded System Technologies, Hyderabad, India","Center for VLSI and Embedded System Technologies, Hyderabad, India#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Center for VLSI and Embedded System Technologies, Hyderabad, India","institution_ids":["https://openalex.org/I64189192"]},{"raw_affiliation_string":"Center for VLSI and Embedded System Technologies, Hyderabad, India#TAB#","institution_ids":["https://openalex.org/I64189192"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110928491","display_name":"M. Kirthi Krishna","orcid":null},"institutions":[{"id":"https://openalex.org/I64189192","display_name":"International Institute of Information Technology, Hyderabad","ror":"https://ror.org/05f11g639","country_code":"IN","type":"education","lineage":["https://openalex.org/I64189192"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"M. Kirthi Krishna","raw_affiliation_strings":["Center for VLSI and Embedded System Technologies, Hyderabad, India","Center for VLSI and Embedded System Technologies, Hyderabad, India#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Center for VLSI and Embedded System Technologies, Hyderabad, India","institution_ids":["https://openalex.org/I64189192"]},{"raw_affiliation_string":"Center for VLSI and Embedded System Technologies, Hyderabad, India#TAB#","institution_ids":["https://openalex.org/I64189192"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101945130","display_name":"M.B. Srinivas","orcid":"https://orcid.org/0000-0003-3820-0561"},"institutions":[{"id":"https://openalex.org/I64189192","display_name":"International Institute of Information Technology, Hyderabad","ror":"https://ror.org/05f11g639","country_code":"IN","type":"education","lineage":["https://openalex.org/I64189192"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"M. B. Srinivas","raw_affiliation_strings":["Center for VLSI and Embedded System Technologies, Hyderabad, India","Center for VLSI and Embedded System Technologies, Hyderabad, India#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Center for VLSI and Embedded System Technologies, Hyderabad, India","institution_ids":["https://openalex.org/I64189192"]},{"raw_affiliation_string":"Center for VLSI and Embedded System Technologies, Hyderabad, India#TAB#","institution_ids":["https://openalex.org/I64189192"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I64189192"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":27,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"188","last_page":"191"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.7801408171653748},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6716514825820923},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6387098431587219},{"id":"https://openalex.org/keywords/transmission-gate","display_name":"Transmission gate","score":0.6177245378494263},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.5607377886772156},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5032843947410583},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.49339404702186584},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.47594738006591797},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4693112373352051},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4646688401699066},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.42940929532051086},{"id":"https://openalex.org/keywords/transmission","display_name":"Transmission (telecommunications)","score":0.42934876680374146},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4100886881351471},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.332258403301239},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3200259506702423},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.31222766637802124},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.29116547107696533},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.247379332780838},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.21841058135032654},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14874163269996643},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1296839416027069},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11816677451133728},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08600819110870361}],"concepts":[{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.7801408171653748},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6716514825820923},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6387098431587219},{"id":"https://openalex.org/C2780949067","wikidata":"https://www.wikidata.org/wiki/Q1136752","display_name":"Transmission gate","level":4,"score":0.6177245378494263},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5607377886772156},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5032843947410583},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.49339404702186584},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.47594738006591797},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4693112373352051},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4646688401699066},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.42940929532051086},{"id":"https://openalex.org/C761482","wikidata":"https://www.wikidata.org/wiki/Q118093","display_name":"Transmission (telecommunications)","level":2,"score":0.42934876680374146},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4100886881351471},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.332258403301239},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3200259506702423},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.31222766637802124},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.29116547107696533},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.247379332780838},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.21841058135032654},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14874163269996643},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1296839416027069},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11816677451133728},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08600819110870361},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1228784.1228833","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1228784.1228833","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8700000047683716,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2130646500","https://openalex.org/W2135700290","https://openalex.org/W2141849037","https://openalex.org/W2144821480","https://openalex.org/W2293347572","https://openalex.org/W3158792238"],"related_works":["https://openalex.org/W3170806431","https://openalex.org/W2357289797","https://openalex.org/W2187717486","https://openalex.org/W1861470194","https://openalex.org/W2095479227","https://openalex.org/W4320030318","https://openalex.org/W2128096982","https://openalex.org/W2807717303","https://openalex.org/W2007403364","https://openalex.org/W2977485606"],"abstract_inverted_index":{"Parallel":[0],"counters":[1,29],"are":[2,36,94],"key":[3],"elements":[4],"in":[5,72,77,103,111],"many":[6],"arithmetic":[7,73],"circuits,":[8],"especially":[9],"fast":[10],"multipliers.":[11],"In":[12],"this":[13],"paper,":[14],"novel":[15],"architectures":[16],"and":[17,27,63,68,80,93,105],"designs":[18,86,92],"for":[19,47],"high":[20,78],"speed,":[21],"low":[22],"power":[23,112],"(3,2),":[24],"(7,3),":[25],"(15,4)":[26],"(31,5)":[28],"capable":[30],"of":[31,61,66,100,108],"operating":[32],"at":[33],"ultra-low":[34],"voltages":[35],"presented.":[37],"Based":[38],"on":[39,58],"these":[40],"counters,":[41],"a":[42,64,106],"generalized":[43],"architecture":[44,55],"is":[45],"derived":[46],"large":[48],"(m,":[49],"n)":[50],"parallel":[51],"counters.":[52],"The":[53,83],"proposed":[54,84],"lays":[56],"emphasis":[57],"the":[59],"use":[60],"multiplexers":[62],"combination":[65],"CMOS":[67],"transmission":[69],"gate":[70],"logic":[71],"circuits":[74],"that":[75],"result":[76],"speed":[79],"efficient":[81],"design.":[82],"counter":[85],"have":[87],"been":[88],"compared":[89],"with":[90],"existing":[91],"shown":[95],"to":[96],"achieve":[97],"an":[98],"improvement":[99],"about":[101,109],"45%":[102],"delay":[104],"reduction":[107],"25%":[110],"consumption.":[113]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
