{"id":"https://openalex.org/W2137799400","doi":"https://doi.org/10.1145/1228784.1228830","title":"An asynchronous fpga logic cell implementation","display_name":"An asynchronous fpga logic cell implementation","publication_year":2007,"publication_date":"2007-03-11","ids":{"openalex":"https://openalex.org/W2137799400","doi":"https://doi.org/10.1145/1228784.1228830","mag":"2137799400"},"language":"en","primary_location":{"id":"doi:10.1145/1228784.1228830","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1228784.1228830","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048458032","display_name":"Atabak Mahram","orcid":null},"institutions":[{"id":"https://openalex.org/I158248296","display_name":"Amirkabir University of Technology","ror":"https://ror.org/04gzbav43","country_code":"IR","type":"education","lineage":["https://openalex.org/I158248296"]}],"countries":["IR"],"is_corresponding":true,"raw_author_name":"Atabak Mahram","raw_affiliation_strings":["Amirkabir University of Technology, Tehran, Iran","Amirkabir University of Technology, Tehran, IRAN"],"affiliations":[{"raw_affiliation_string":"Amirkabir University of Technology, Tehran, Iran","institution_ids":["https://openalex.org/I158248296"]},{"raw_affiliation_string":"Amirkabir University of Technology, Tehran, IRAN","institution_ids":["https://openalex.org/I158248296"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069865058","display_name":"Mehrdad Najibi","orcid":null},"institutions":[{"id":"https://openalex.org/I158248296","display_name":"Amirkabir University of Technology","ror":"https://ror.org/04gzbav43","country_code":"IR","type":"education","lineage":["https://openalex.org/I158248296"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Mehrdad Najibi","raw_affiliation_strings":["Amirkabir University of Technology, Tehran, Iran","Amirkabir University of Technology, Tehran, IRAN"],"affiliations":[{"raw_affiliation_string":"Amirkabir University of Technology, Tehran, Iran","institution_ids":["https://openalex.org/I158248296"]},{"raw_affiliation_string":"Amirkabir University of Technology, Tehran, IRAN","institution_ids":["https://openalex.org/I158248296"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5085021768","display_name":"Hossein Pedram","orcid":"https://orcid.org/0000-0002-2331-0568"},"institutions":[{"id":"https://openalex.org/I158248296","display_name":"Amirkabir University of Technology","ror":"https://ror.org/04gzbav43","country_code":"IR","type":"education","lineage":["https://openalex.org/I158248296"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Hossein Pedram","raw_affiliation_strings":["Amirkabir University of Technology, Tehran, Iran","Amirkabir University of Technology, Tehran, IRAN"],"affiliations":[{"raw_affiliation_string":"Amirkabir University of Technology, Tehran, Iran","institution_ids":["https://openalex.org/I158248296"]},{"raw_affiliation_string":"Amirkabir University of Technology, Tehran, IRAN","institution_ids":["https://openalex.org/I158248296"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5048458032"],"corresponding_institution_ids":["https://openalex.org/I158248296"],"apc_list":null,"apc_paid":null,"fwci":0.7025,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.74932875,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"176","last_page":"179"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7513943910598755},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.730003297328949},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.6819485425949097},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.6605210304260254},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6414287090301514},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.637500524520874},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6366123557090759},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.5663247108459473},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5615522265434265},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.5362464785575867},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.5227765440940857},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5036434531211853},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.4839918613433838},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.4775705933570862},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.44686925411224365},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.43476197123527527},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.4118392765522003},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.40837377309799194},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3398158550262451},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.29519104957580566},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.2880910634994507},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.26437807083129883},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.20893201231956482},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10547205805778503},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.0709456205368042},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.06776416301727295}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7513943910598755},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.730003297328949},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.6819485425949097},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.6605210304260254},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6414287090301514},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.637500524520874},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6366123557090759},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.5663247108459473},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5615522265434265},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.5362464785575867},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5227765440940857},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5036434531211853},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.4839918613433838},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.4775705933570862},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.44686925411224365},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43476197123527527},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.4118392765522003},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.40837377309799194},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3398158550262451},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.29519104957580566},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.2880910634994507},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.26437807083129883},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.20893201231956482},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10547205805778503},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0709456205368042},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.06776416301727295},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1228784.1228830","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1228784.1228830","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.4399999976158142}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W16511050","https://openalex.org/W1523051745","https://openalex.org/W1615690992","https://openalex.org/W1657311214","https://openalex.org/W2113645429","https://openalex.org/W2128723913","https://openalex.org/W2150872535","https://openalex.org/W2487142227","https://openalex.org/W2544832035"],"related_works":["https://openalex.org/W2994343469","https://openalex.org/W3129977055","https://openalex.org/W3105918491","https://openalex.org/W1905312773","https://openalex.org/W2386022279","https://openalex.org/W2373127312","https://openalex.org/W2197466303","https://openalex.org/W2356140560","https://openalex.org/W2534530934","https://openalex.org/W4372324531"],"abstract_inverted_index":{"We":[0],"present":[1],"a":[2,56,87,96,110],"new":[3],"method":[4,58,64,94],"for":[5,59],"implementing":[6,60],"asynchronous":[7],"FPGA":[8],"logic":[9,25,32,43,89,99],"cells":[10,26],"which":[11,34],"are":[12],"configurable":[13],"at":[14],"pipeline":[15],"level.":[16],"Previous":[17],"implementations":[18],"of":[19,23,41],"the":[20,30,39,42,47],"basic":[21],"elements":[22],"these":[24,61],"were":[27],"based":[28],"on":[29,38],"pre-charged":[31],"implementation":[33],"imposes":[35],"some":[36],"limitations":[37],"size":[40],"cell":[44,90,100],"due":[45],"to":[46],"stacking":[48,75],"problem.":[49],"To":[50],"overcome":[51],"this":[52,93],"limitation":[53],"we":[54],"propose":[55],"novel":[57],"templates.":[62],"Our":[63],"uses":[65],"standard":[66],"single-rail":[67],"computational":[68],"circuits.":[69],"It":[70],"does":[71],"not":[72,79],"have":[73],"any":[74],"problem":[76],"and":[77,105],"is":[78],"limited":[80],"in":[81,103,107],"size.":[82],"The":[83],"results":[84],"show":[85],"that":[86],"4-input":[88],"implemented":[91],"by":[92,101],"outperforms":[95],"previous":[97],"3-input":[98],"16%":[102],"speed":[104],"29%":[106],"power":[108],"with":[109],"negligible":[111],"area":[112],"overhead.":[113]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
