{"id":"https://openalex.org/W2133819978","doi":"https://doi.org/10.1145/1228784.1228815","title":"Operation limits in RTD-based ternary quantizers","display_name":"Operation limits in RTD-based ternary quantizers","publication_year":2007,"publication_date":"2007-03-11","ids":{"openalex":"https://openalex.org/W2133819978","doi":"https://doi.org/10.1145/1228784.1228815","mag":"2133819978"},"language":"en","primary_location":{"id":"doi:10.1145/1228784.1228815","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1228784.1228815","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101455624","display_name":"Juan N\u00fa\u00f1ez","orcid":"https://orcid.org/0000-0002-0279-9472"},"institutions":[{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]},{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Juan N\u00fa\u00f1ez","raw_affiliation_strings":["IMSE-CNM-CSIC and Universidad de Sevilla, Seville, DC, Spain","IMSE-CNM-CSIC and Universidad de Sevilla, Seville, DC, Spain#TAB#"],"affiliations":[{"raw_affiliation_string":"IMSE-CNM-CSIC and Universidad de Sevilla, Seville, DC, Spain","institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"]},{"raw_affiliation_string":"IMSE-CNM-CSIC and Universidad de Sevilla, Seville, DC, Spain#TAB#","institution_ids":["https://openalex.org/I79238269"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054229228","display_name":"Jos\u00e9 M. Quintana","orcid":"https://orcid.org/0000-0003-2170-7876"},"institutions":[{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]},{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Jos\u00e9 M. Quintana","raw_affiliation_strings":["IMSE-CNM-CSIC and Universidad de Sevilla, Seville, DC, Spain","IMSE-CNM-CSIC and Universidad de Sevilla, Seville, DC, Spain#TAB#"],"affiliations":[{"raw_affiliation_string":"IMSE-CNM-CSIC and Universidad de Sevilla, Seville, DC, Spain","institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"]},{"raw_affiliation_string":"IMSE-CNM-CSIC and Universidad de Sevilla, Seville, DC, Spain#TAB#","institution_ids":["https://openalex.org/I79238269"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5031060766","display_name":"M.J. Avedillo","orcid":"https://orcid.org/0000-0002-8345-8441"},"institutions":[{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]},{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Mar\u00eda J. Avedillo","raw_affiliation_strings":["IMSE-CNM-CSIC and Universidad de Sevilla, Seville, DC, Spain","IMSE-CNM-CSIC and Universidad de Sevilla, Seville, DC, Spain#TAB#"],"affiliations":[{"raw_affiliation_string":"IMSE-CNM-CSIC and Universidad de Sevilla, Seville, DC, Spain","institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"]},{"raw_affiliation_string":"IMSE-CNM-CSIC and Universidad de Sevilla, Seville, DC, Spain#TAB#","institution_ids":["https://openalex.org/I79238269"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5101455624"],"corresponding_institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.16090561,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"114","last_page":"119"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10682","display_name":"Quantum Computing Algorithms and Architecture","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/ternary-operation","display_name":"Ternary operation","score":0.7128533720970154},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.622404158115387},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5844710469245911},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5656813979148865},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.513433575630188},{"id":"https://openalex.org/keywords/multivibrator","display_name":"Multivibrator","score":0.5012021064758301},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44416141510009766},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3607980012893677},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3302863836288452},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1916426122188568},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1794780194759369}],"concepts":[{"id":"https://openalex.org/C64452783","wikidata":"https://www.wikidata.org/wiki/Q1524945","display_name":"Ternary operation","level":2,"score":0.7128533720970154},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.622404158115387},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5844710469245911},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5656813979148865},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.513433575630188},{"id":"https://openalex.org/C198537423","wikidata":"https://www.wikidata.org/wiki/Q259838","display_name":"Multivibrator","level":3,"score":0.5012021064758301},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44416141510009766},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3607980012893677},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3302863836288452},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1916426122188568},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1794780194759369},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1228784.1228815","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1228784.1228815","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1605635714","https://openalex.org/W2119923518","https://openalex.org/W2126099198","https://openalex.org/W2128725931","https://openalex.org/W2135436810","https://openalex.org/W2162146242","https://openalex.org/W2172071777"],"related_works":["https://openalex.org/W2045825909","https://openalex.org/W2366528284","https://openalex.org/W2367958769","https://openalex.org/W2088179597","https://openalex.org/W2347686112","https://openalex.org/W2389120046","https://openalex.org/W849517562","https://openalex.org/W2530579256","https://openalex.org/W2033190772","https://openalex.org/W2127337382"],"abstract_inverted_index":{"Multiple-valued":[0],"Logic":[1,15],"(MVL)":[2],"circuits":[3,25],"are":[4,19],"one":[5],"of":[6,11,23,46],"the":[7,12,21,36,44,53],"most":[8],"attractive":[9],"applications":[10],"Monostable-to-Multistable":[13],"transition":[14],"(MML),":[16],"and":[17,51],"they":[18],"on":[20],"basis":[22],"advanced":[24],"for":[26],"communications.":[27],"However,":[28],"a":[29,63],"proper":[30],"design":[31],"is":[32],"not":[33],"inherent":[34],"to":[35,61],"usual":[37],"MML":[38,48],"circuit":[39,56],"topologies.":[40],"This":[41],"paper":[42],"analyses":[43],"case":[45],"an":[47],"ternary":[49],"quantizer,":[50],"determines":[52],"relations":[54],"that":[55],"representative":[57],"parameters":[58],"must":[59],"verify":[60],"obtain":[62],"correct":[64],"DC":[65],"operation.":[66]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}