{"id":"https://openalex.org/W2169480831","doi":"https://doi.org/10.1145/1228784.1228803","title":"SEU mitigation for sram-based fpgas through dynamic partial reconfiguration","display_name":"SEU mitigation for sram-based fpgas through dynamic partial reconfiguration","publication_year":2007,"publication_date":"2007-03-11","ids":{"openalex":"https://openalex.org/W2169480831","doi":"https://doi.org/10.1145/1228784.1228803","mag":"2169480831"},"language":"en","primary_location":{"id":"doi:10.1145/1228784.1228803","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1228784.1228803","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014159983","display_name":"Cristiana Bolchini","orcid":"https://orcid.org/0000-0001-5065-7906"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Cristiana Bolchini","raw_affiliation_strings":["Politecnico di Milano, Milano, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058990044","display_name":"Davide Quarta","orcid":null},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Davide Quarta","raw_affiliation_strings":["Politecnico di Milano, Milano, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010543929","display_name":"Marco D. Santambrogio","orcid":"https://orcid.org/0000-0002-9883-9693"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Marco D. Santambrogio","raw_affiliation_strings":["Politecnico di Milano, Milano, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I93860229"],"apc_list":null,"apc_paid":null,"fwci":5.4903,"has_fulltext":false,"cited_by_count":40,"citation_normalized_percentile":{"value":0.9685374,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"55","last_page":"60"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.925576388835907},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.8734986782073975},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8306977152824402},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7095683813095093},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6616993546485901},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.5870031118392944},{"id":"https://openalex.org/keywords/single-event-upset","display_name":"Single event upset","score":0.42347899079322815},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.24934208393096924}],"concepts":[{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.925576388835907},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.8734986782073975},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8306977152824402},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7095683813095093},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6616993546485901},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.5870031118392944},{"id":"https://openalex.org/C2780073065","wikidata":"https://www.wikidata.org/wiki/Q1476733","display_name":"Single event upset","level":3,"score":0.42347899079322815},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.24934208393096924},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1228784.1228803","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1228784.1228803","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"},{"id":"pmh:oai:re.public.polimi.it:11311/268100","is_oa":false,"landing_page_url":"http://hdl.handle.net/11311/268100","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W48552920","https://openalex.org/W261177573","https://openalex.org/W1504339380","https://openalex.org/W1572474464","https://openalex.org/W1581761235","https://openalex.org/W1970885193","https://openalex.org/W2033346530","https://openalex.org/W2050431855","https://openalex.org/W2099329957","https://openalex.org/W2108942153","https://openalex.org/W2119901643","https://openalex.org/W2135743241","https://openalex.org/W2157009629","https://openalex.org/W2165297788","https://openalex.org/W4251551684","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W2808484818","https://openalex.org/W2810427553","https://openalex.org/W2135053878","https://openalex.org/W2941434274","https://openalex.org/W2340647897","https://openalex.org/W4249632163","https://openalex.org/W2797161794","https://openalex.org/W2073075351","https://openalex.org/W2096938998","https://openalex.org/W1760305469"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,75,118],"methodology":[4,116],"for":[5],"designing":[6],"reliable":[7],"systems":[8],"implemented":[9],"on":[10],"Field":[11],"Programmable":[12],"Gate":[13],"Arrays":[14],"(FPGAs),":[15],"able":[16],"to":[17,41,61,69,73,84,104,117,123],"cope":[18],"with":[19],"the":[20,43,49,54,63,80,91,102,106,112,115,125],"effects":[21,44],"of":[22,45,65,77,79,93,111,114],"Single":[23],"Event":[24],"Upset":[25],"(SEU)":[26],"faults,":[27],"causing":[28],"bit-flips":[29],"in":[30,82],"SRAM":[31,51],"memory.":[32],"The":[33,58,88],"approach":[34],"exploits":[35],"FPGAs'":[36],"partial":[37],"dynamic":[38],"re-configuration":[39],"capability":[40],"mitigate":[42],"SEUs,":[46],"affecting":[47],"either":[48,68],"user":[50],"memory":[52,56],"or":[53,72],"configuration":[55],"itself.":[57],"goal":[59],"is":[60],"detect":[62],"occurrence":[64],"faults":[66],"and":[67,99],"restart":[70],"computation":[71],"trigger":[74],"reconfiguration":[76],"part":[78],"device":[81],"order":[83],"recover":[85],"from":[86],"them.":[87],"proposal":[89],"allows":[90],"exploration":[92],"different":[94],"solutions,":[95],"characterized":[96],"byvarying":[97],"costs":[98],"benefits,":[100],"allowing":[101],"designer":[103],"select":[105],"most":[107],"convenient":[108],"trade-off.":[109],"Results":[110],"application":[113],"case":[119],"study":[120],"are":[121],"reported":[122],"evaluate":[124],"proposed":[126],"approach.":[127]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2015,"cited_by_count":5},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":6}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}