{"id":"https://openalex.org/W2096227207","doi":"https://doi.org/10.1145/1216919.1216949","title":"Parametric yield in FPGAs due to within-die delay variations","display_name":"Parametric yield in FPGAs due to within-die delay variations","publication_year":2007,"publication_date":"2007-02-18","ids":{"openalex":"https://openalex.org/W2096227207","doi":"https://doi.org/10.1145/1216919.1216949","mag":"2096227207"},"language":"en","primary_location":{"id":"doi:10.1145/1216919.1216949","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1216919.1216949","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048050040","display_name":"Pete Sedcole","orcid":null},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Pete Sedcole","raw_affiliation_strings":["Imperial College London, UK","Imperial College , London, UK"],"affiliations":[{"raw_affiliation_string":"Imperial College London, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Imperial College , London, UK","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091532722","display_name":"Peter Y. K. Cheung","orcid":"https://orcid.org/0000-0002-8236-1816"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Peter Y. K. Cheung","raw_affiliation_strings":["Imperial College London, UK","Imperial College , London, UK"],"affiliations":[{"raw_affiliation_string":"Imperial College London, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Imperial College , London, UK","institution_ids":["https://openalex.org/I47508984"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5048050040"],"corresponding_institution_ids":["https://openalex.org/I47508984"],"apc_list":null,"apc_paid":null,"fwci":7.0249,"has_fulltext":false,"cited_by_count":31,"citation_normalized_percentile":{"value":0.97137066,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"178","last_page":"187"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.78896564245224},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.7206194400787354},{"id":"https://openalex.org/keywords/parametric-statistics","display_name":"Parametric statistics","score":0.667790949344635},{"id":"https://openalex.org/keywords/die","display_name":"Die (integrated circuit)","score":0.5652214288711548},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5319742560386658},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.44503557682037354},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.43089744448661804},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4256362318992615},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3647908568382263},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2947806715965271},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2747707962989807},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.17455193400382996},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.15154632925987244}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.78896564245224},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.7206194400787354},{"id":"https://openalex.org/C117251300","wikidata":"https://www.wikidata.org/wiki/Q1849855","display_name":"Parametric statistics","level":2,"score":0.667790949344635},{"id":"https://openalex.org/C111106434","wikidata":"https://www.wikidata.org/wiki/Q1072430","display_name":"Die (integrated circuit)","level":2,"score":0.5652214288711548},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5319742560386658},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.44503557682037354},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.43089744448661804},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4256362318992615},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3647908568382263},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2947806715965271},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2747707962989807},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.17455193400382996},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.15154632925987244},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1216919.1216949","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1216919.1216949","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.4099999964237213}],"awards":[],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1525409241","https://openalex.org/W1526642634","https://openalex.org/W1532888190","https://openalex.org/W1984105700","https://openalex.org/W1987383141","https://openalex.org/W2084083833","https://openalex.org/W2114131053","https://openalex.org/W2115596773","https://openalex.org/W2123355738","https://openalex.org/W2129883611","https://openalex.org/W2141682861","https://openalex.org/W2143901474","https://openalex.org/W2150107614","https://openalex.org/W2154665706","https://openalex.org/W2154776455","https://openalex.org/W2155042027","https://openalex.org/W2161344439","https://openalex.org/W2163262735","https://openalex.org/W2165740397","https://openalex.org/W2532498749","https://openalex.org/W6631407737"],"related_works":["https://openalex.org/W2808484818","https://openalex.org/W2810427553","https://openalex.org/W2135053878","https://openalex.org/W2941434274","https://openalex.org/W2340647897","https://openalex.org/W4249632163","https://openalex.org/W1760305469","https://openalex.org/W2797161794","https://openalex.org/W2073075351","https://openalex.org/W2096938998"],"abstract_inverted_index":{"Variations":[0],"in":[1,7,9,50,92],"the":[2,14,30,53],"semiconductor":[3],"fabrication":[4],"process":[5],"results":[6],"variability":[8,49],"parameters":[10],"between":[11],"transistors":[12],"on":[13],"same":[15],"die,":[16],"a":[17,66],"problem":[18],"exacerbated":[19],"by":[20,108],"lithographic":[21],"scaling.":[22],"The":[23,68],"re-configurability":[24],"of":[25,70],"Field-Programmable":[26],"Gate":[27],"Arrays":[28],"presents":[29,40],"opportunity":[31],"to":[32],"compensate":[33],"for":[34,44],"within-die":[35,46],"delay":[36,48],"variability.":[37],"This":[38],"paper":[39],"three":[41],"reconfiguration-based":[42,110],"strategies":[43],"compensating":[45],"stochastic":[47],"FPGAs:":[51],"reconfiguring":[52,62],"entire":[54],"FPGA,":[55,60],"relocating":[56],"subcircuits":[57],"within":[58,65],"an":[59],"and":[61,75,80,95,102],"signal":[63],"paths":[64],"design.":[67],"yield":[69,94],"each":[71],"strategy":[72],"is":[73,87],"analysed":[74],"compared":[76],"with":[77],"worst-case":[78],"design":[79],"statistical":[81],"static":[82],"timing":[83,96],"analysis":[84],"(SSTA).":[85],"It":[86],"demonstrated":[88],"that":[89],"significant":[90],"im-provements":[91],"circuit":[93],"are":[97],"possible":[98],"using":[99],"SSTA":[100],"alone,":[101],"these":[103],"improvements":[104],"can":[105],"be":[106],"enhanced":[107],"employing":[109],"techniques.":[111]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
