{"id":"https://openalex.org/W2056869818","doi":"https://doi.org/10.1145/1216919.1216941","title":"Integrating FPGAs in high-performance computing","display_name":"Integrating FPGAs in high-performance computing","publication_year":2007,"publication_date":"2007-02-18","ids":{"openalex":"https://openalex.org/W2056869818","doi":"https://doi.org/10.1145/1216919.1216941","mag":"2056869818"},"language":"en","primary_location":{"id":"doi:10.1145/1216919.1216941","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1216919.1216941","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024935114","display_name":"Nathan D. Woods","orcid":"https://orcid.org/0000-0002-1082-2396"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Nathan Woods","raw_affiliation_strings":["XtremeData Inc., Schaumburg, IL"],"affiliations":[{"raw_affiliation_string":"XtremeData Inc., Schaumburg, IL","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5024935114"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6333,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.70692912,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"132","last_page":"132"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9664999842643738,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/coprocessor","display_name":"Coprocessor","score":0.8516461849212646},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7905413508415222},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7792493104934692},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6994407176971436},{"id":"https://openalex.org/keywords/motherboard","display_name":"Motherboard","score":0.6906073689460754},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.6033221483230591},{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.5664200186729431},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4901803135871887},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.41811811923980713},{"id":"https://openalex.org/keywords/x86","display_name":"x86","score":0.41764628887176514},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4140453040599823},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.40839725732803345},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.14341619610786438}],"concepts":[{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.8516461849212646},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7905413508415222},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7792493104934692},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6994407176971436},{"id":"https://openalex.org/C2777697265","wikidata":"https://www.wikidata.org/wiki/Q4321","display_name":"Motherboard","level":2,"score":0.6906073689460754},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.6033221483230591},{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.5664200186729431},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4901803135871887},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.41811811923980713},{"id":"https://openalex.org/C170723468","wikidata":"https://www.wikidata.org/wiki/Q182933","display_name":"x86","level":3,"score":0.41764628887176514},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4140453040599823},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.40839725732803345},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.14341619610786438}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1216919.1216941","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1216919.1216941","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4399999976158142,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2189125857","https://openalex.org/W2166124169","https://openalex.org/W2160035739","https://openalex.org/W4256272048","https://openalex.org/W1980352715","https://openalex.org/W2160342394","https://openalex.org/W2185423317","https://openalex.org/W2090940121","https://openalex.org/W2056869818","https://openalex.org/W2020410665"],"abstract_inverted_index":{"Today,":[0],"many":[1],"enterprises":[2],"are":[3],"evaluating":[4],"and":[5,51,92,118,200,234,236],"in":[6,254],"some":[7,15],"cases":[8],"deploying":[9],"heterogeneous":[10],"computing":[11,28,65,87],"platforms":[12],"that":[13,67,77],"include":[14,196],"form":[16],"of":[17,26,63,97,104,120,146,172,213,245],"hardware":[18,32,53],"acceleration":[19],"or":[20],"co-processing.":[21],"Such":[22],"systems":[23,106],"typically":[24],"consist":[25],"commodity":[27],"clusters":[29],"augmented":[30],"by":[31,143],"accelerators":[33],"like":[34,47],"graphics":[35],"processing":[36],"units":[37],"(GPUs),":[38],"field":[39],"programmable":[40],"gate":[41],"arrays":[42],"(FPGAs),":[43],"gaming":[44],"platform":[45,66],"chips":[46],"the":[48,98,102,114,126,147,151,162,187,211,221,224,229,249],"Cell":[49],"Processor,":[50],"other":[52,158],"accelerators.In":[54],"this":[55],"presentation":[56,99],"we":[57],"will":[58,100,112],"identify":[59],"desirable":[60],"architectural":[61,194],"features":[62],"a":[64,84,108,121,135,140,246],"includes":[68],"FPGA":[69,82,124,138,152,176,232],"co-processing,":[70],"along":[71],"with":[72,150,157,169,180],"practical":[73],"system":[74,142,247],"design":[75],"issues":[76],"arise":[78],"when":[79],"introducing":[80],"an":[81,190],"into":[83,139],"modern":[85],"x86":[86],"blade,":[88],"including":[89],"mechanical,":[90],"power":[91],"cooling":[93],"issues.The":[94],"main":[95],"body":[96],"highlight":[101],"promise":[103],"these":[105],"using":[107],"concrete":[109],"example.":[110],"I":[111],"describe":[113],"architecture,":[115],"technical":[116],"capabilities,":[117],"limitations":[119],"commercially":[122],"available":[123],"coprocessor,":[125],"XD1000\u2122":[127],"coprocessor":[128,177,222,225,251],"module":[129,155],"from":[130],"XtremeData.":[131],"The":[132,154,175],"XD1000":[133,250],"integrates":[134],"Stratix\u2122":[136],"II":[137],"multi-Opteron\u2122":[141],"replacing":[144],"one":[145],"Opteron":[148,159],"CPUs":[149,160],"co-processor.":[153],"communicates":[156],"on":[161,220],"motherboard":[163,181],"via":[164],"point-to-point":[165],"HyperTransport":[166],"(HT)":[167],"links":[168],"3.2":[170],"GB/sec":[171],"bandwidth":[173],"each.":[174],"interfaces":[178],"directly":[179],"DDR":[182],"SDRAM":[183],"memory":[184,207],"DIMMs":[185],"without":[186],"need":[188],"for":[189,228,239],"intervening":[191],"north":[192],"bridge.Important":[193],"considerations":[195],"whether":[197],"to":[198,202,204],"provide":[199],"how":[201],"interface":[203,227],"local":[205],"on-module":[206,209],"(e.g.":[208],"SRAM),":[210],"ramifications":[212],"coherent":[214],"vs.":[215],"noncoherent":[216],"HT":[217],"protocol":[218],"support":[219,238],"module,":[223],"programming":[226],"host":[230],"system,":[231],"configuration,":[233],"monitoring":[235],"test":[237],"user":[240],"debug.":[241],"A":[242],"block":[243],"diagram":[244],"employing":[248],"is":[252],"shown":[253],"Figure":[255],"1.":[256]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
