{"id":"https://openalex.org/W1970544797","doi":"https://doi.org/10.1145/1216919.1216938","title":"High-level languages","display_name":"High-level languages","publication_year":2007,"publication_date":"2007-02-18","ids":{"openalex":"https://openalex.org/W1970544797","doi":"https://doi.org/10.1145/1216919.1216938","mag":"1970544797"},"language":"en","primary_location":{"id":"doi:10.1145/1216919.1216938","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1216919.1216938","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109079559","display_name":"Mike Wirthlin","orcid":null},"institutions":[{"id":"https://openalex.org/I100005738","display_name":"Brigham Young University","ror":"https://ror.org/047rhhm47","country_code":"US","type":"education","lineage":["https://openalex.org/I100005738"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Mike Wirthlin","raw_affiliation_strings":["Brigham Young University"],"affiliations":[{"raw_affiliation_string":"Brigham Young University","institution_ids":["https://openalex.org/I100005738"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086958474","display_name":"Misha Burich","orcid":null},"institutions":[{"id":"https://openalex.org/I4210094575","display_name":"Altera (United Kingdom)","ror":"https://ror.org/00m96gg93","country_code":"GB","type":"company","lineage":["https://openalex.org/I4210094575"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Misha Burich","raw_affiliation_strings":["Altera"],"affiliations":[{"raw_affiliation_string":"Altera","institution_ids":["https://openalex.org/I4210094575"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017640227","display_name":"Andrew Guyler","orcid":null},"institutions":[{"id":"https://openalex.org/I4210099704","display_name":"Mentor","ror":"https://ror.org/016grqh48","country_code":"GB","type":"nonprofit","lineage":["https://openalex.org/I4210099704"]},{"id":"https://openalex.org/I105695857","display_name":"Siemens (Hungary)","ror":"https://ror.org/01rk7mv85","country_code":"HU","type":"company","lineage":["https://openalex.org/I105695857","https://openalex.org/I1325886976"]}],"countries":["GB","HU"],"is_corresponding":false,"raw_author_name":"Andrew Guyler","raw_affiliation_strings":["Mentor Graphics","(Mentor Graphics)"],"affiliations":[{"raw_affiliation_string":"Mentor Graphics","institution_ids":["https://openalex.org/I105695857","https://openalex.org/I4210099704"]},{"raw_affiliation_string":"(Mentor Graphics)","institution_ids":["https://openalex.org/I105695857","https://openalex.org/I4210099704"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5014679580","display_name":"Brian Von Herzen","orcid":"https://orcid.org/0000-0002-8144-1654"},"institutions":[{"id":"https://openalex.org/I4210088314","display_name":"Prototypes (United States)","ror":"https://ror.org/007mg2f66","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088314"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Brian Von Herzen","raw_affiliation_strings":["Rapid Prototypes"],"affiliations":[{"raw_affiliation_string":"Rapid Prototypes","institution_ids":["https://openalex.org/I4210088314"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5109079559"],"corresponding_institution_ids":["https://openalex.org/I100005738"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.05666567,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"127","last_page":"127"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9868999719619751,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9864000082015991,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8102184534072876},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6686282157897949},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6402341723442078},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.5705904960632324},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5472549796104431},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.5136331915855408},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.4886985123157501},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4661594331264496},{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.4625204801559448},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.4437875747680664},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4159359335899353},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3095521926879883}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8102184534072876},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6686282157897949},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6402341723442078},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.5705904960632324},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5472549796104431},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.5136331915855408},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.4886985123157501},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4661594331264496},{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.4625204801559448},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.4437875747680664},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4159359335899353},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3095521926879883}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1216919.1216938","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1216919.1216938","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2752828786","https://openalex.org/W1984090905","https://openalex.org/W2242433395","https://openalex.org/W2544073398","https://openalex.org/W2548514518","https://openalex.org/W2579932084","https://openalex.org/W4233602124","https://openalex.org/W2156965212","https://openalex.org/W1603163876","https://openalex.org/W2133642747"],"abstract_inverted_index":{"There":[0],"are":[1,148,168,187,226,269],"several":[2],"interesting":[3],"compilation":[4],"tools":[5,18,48,76,92,147,225,257,271],"on":[6,319],"the":[7,20,57,80,111,115,141,153,172,179,200,245,249,260,284,338],"market":[8],"for":[9,340],"synthesizing":[10],"FPGA":[11,25,112,127,252,286,304],"circuits":[12,26,203],"from":[13,27,43,293,300],"\"high\"":[14],"level":[15],"languages.":[16],"These":[17,47],"advertise":[19],"ability":[21],"to":[22,59,123,170,183,194,237,244],"generate":[23],"high-quality":[24,126],"a":[28,125,138,211,294,313],"variety":[29,295],"of":[30,64,114,140,156,191,251,296,316],"specification":[31],"formats":[32],"such":[33],"procedural":[34,164],"languages":[35,40,165],"(C,":[36],"Fortran,":[37],"etc.),":[38],"modeling":[39],"(SystemC),":[41],"or":[42,220],"signal":[44],"flow":[45],"graphs.":[46],"claim":[49,72],"significant":[50],"improvements":[51],"in":[52,152,176,196],"design":[53,83,96,100,132,159,256],"productivity":[54,261],"by":[55,205,323],"allowing":[56],"designer":[58,113],"operate":[60],"at":[61],"higher":[62],"levels":[63],"abstraction":[65],"than":[66],"available":[67,175],"with":[68,86,229,241],"traditional":[69],"RTL-level":[70],"synthesis.Some":[71],"that":[73,90,110,145,163,264],"these":[74,91,146,206,270,280],"high-level":[75,158,212,224,301],"will":[77,93,101,117,136,234,278,290,311,336],"completely":[78],"change":[79],"way":[81],"we":[82],"FPGAs.":[84],"Those":[85],"this":[87,197,230,320],"view":[88,231],"believe":[89,109,144,232],"replace":[94],"today's":[95],"approaches":[97],"and":[98,262,282,306,325,333,343],"VHDL/Verilog":[99],"\"wither":[102],"away\"":[103],"like":[104,166],"assembly":[105],"language":[106],"programming.":[107],"They":[108,161],"future":[116,250,285],"only":[118],"need":[119],"basic":[120],"programming":[121],"skills":[122],"create":[124],"designs.":[128],"The":[129,288],"arcane":[130],"RTL":[131],"methodology":[133],"used":[134],"today":[135],"be":[137,235],"thing":[139],"past.":[142],"Others":[143],"just":[149,272],"another":[150,273],"fad":[151],"long":[154],"line":[155],"failed":[157],"tools.":[160,207],"suggest":[162],"C":[167],"ill-suited":[169],"express":[171],"fine-grain":[173],"parallelism":[174],"hardware.":[177],"Further,":[178],"synchronization/timing":[180],"semantics":[181],"needed":[182],"implement":[184],"parallel":[185],"hardware":[186],"not":[188],"available.":[189],"Perhaps":[190],"most":[192],"concern":[193],"those":[195,228],"camp":[198],"is":[199,210,248,330],"lower":[201],"quality":[202,263],"synthesized":[204],"What":[208],"good":[209],"tool":[213,302],"if":[214],"it":[215],"can't":[216],"meet":[217],"your":[218],"timing":[219],"performance":[221],"constraint?":[222],"If":[223],"successful,":[227],"they":[233],"limited":[236,242],"small":[238],"niche":[239],"markets":[240],"appeal":[243],"average":[246],"designer.What":[247],"design?":[253],"Will":[254],"higher-level":[255],"finally":[258],"provide":[259],"has":[265],"been":[266],"promised?":[267],"Or,":[268],"passing":[274],"fad?":[275],"This":[276],"panel":[277,289],"address":[279],"questions":[281,324,342],"discuss":[283],"design.":[287],"include":[291],"experts":[292],"perspectives":[297],"including":[298],"representatives":[299],"vendors,":[303],"manufacturers,":[305],"experienced":[307],"designers.":[308],"Each":[309],"panelist":[310],"give":[312],"brief":[314],"summary":[315],"their":[317],"views":[318],"topic,":[321],"followed":[322],"lively":[326],"debate.":[327],"Audience":[328],"participation":[329],"actively":[331],"encouraged":[332],"audience":[334],"members":[335],"have":[337],"opportunity":[339],"asking":[341],"making":[344],"statements.":[345]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}