{"id":"https://openalex.org/W2160181362","doi":"https://doi.org/10.1145/1216919.1216930","title":"Variation-aware routing for FPGAs","display_name":"Variation-aware routing for FPGAs","publication_year":2007,"publication_date":"2007-02-18","ids":{"openalex":"https://openalex.org/W2160181362","doi":"https://doi.org/10.1145/1216919.1216930","mag":"2160181362"},"language":"en","primary_location":{"id":"doi:10.1145/1216919.1216930","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1216919.1216930","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025849840","display_name":"Satish Sivaswamy","orcid":null},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Satish Sivaswamy","raw_affiliation_strings":["University of Minnesota, MN"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Minnesota, MN","institution_ids":["https://openalex.org/I130238516"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013257804","display_name":"Kia Bazargan","orcid":"https://orcid.org/0000-0003-3624-7366"},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kia Bazargan","raw_affiliation_strings":["University of Minnesota, MN"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Minnesota, MN","institution_ids":["https://openalex.org/I130238516"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I130238516"],"apc_list":null,"apc_paid":null,"fwci":6.1065,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":{"value":0.96515301,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"71","last_page":"79"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.8666033148765564},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8477331399917603},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.8218950033187866},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.8117259740829468},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7000914812088013},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6808419227600098},{"id":"https://openalex.org/keywords/variation","display_name":"Variation (astronomy)","score":0.6477762460708618},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.49483364820480347},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4688374102115631},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.45942237973213196},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44083619117736816},{"id":"https://openalex.org/keywords/network-routing","display_name":"Network routing","score":0.42654740810394287},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.11044549942016602},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.060293048620224}],"concepts":[{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.8666033148765564},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8477331399917603},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.8218950033187866},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.8117259740829468},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7000914812088013},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6808419227600098},{"id":"https://openalex.org/C2778334786","wikidata":"https://www.wikidata.org/wiki/Q1586270","display_name":"Variation (astronomy)","level":2,"score":0.6477762460708618},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.49483364820480347},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4688374102115631},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.45942237973213196},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44083619117736816},{"id":"https://openalex.org/C2983435990","wikidata":"https://www.wikidata.org/wiki/Q22725","display_name":"Network routing","level":3,"score":0.42654740810394287},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.11044549942016602},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.060293048620224},{"id":"https://openalex.org/C44870925","wikidata":"https://www.wikidata.org/wiki/Q37547","display_name":"Astrophysics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1216919.1216930","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1216919.1216930","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.62.1761","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.62.1761","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ece.umn.edu/users/kia/Papers/2007/fpga07_ssta_router.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1511688816","https://openalex.org/W1523051745","https://openalex.org/W1693570377","https://openalex.org/W1997797456","https://openalex.org/W2024146094","https://openalex.org/W2084083833","https://openalex.org/W2097175306","https://openalex.org/W2110687226","https://openalex.org/W2115596773","https://openalex.org/W2119125081","https://openalex.org/W2132554587","https://openalex.org/W2136328167","https://openalex.org/W2139637699","https://openalex.org/W2148694408","https://openalex.org/W2158750015","https://openalex.org/W2163262735","https://openalex.org/W4210605217","https://openalex.org/W4253899153","https://openalex.org/W4292023222","https://openalex.org/W6631410163","https://openalex.org/W6671839961"],"related_works":["https://openalex.org/W1965055688","https://openalex.org/W2130626635","https://openalex.org/W4250593837","https://openalex.org/W2081591578","https://openalex.org/W3200538824","https://openalex.org/W1977643363","https://openalex.org/W3152386622","https://openalex.org/W2014162718","https://openalex.org/W2140896055","https://openalex.org/W2123184590"],"abstract_inverted_index":{"Chip":[0],"design":[1],"in":[2,72],"the":[3,23,31,40,51,67,70,74,88,94,100,104],"nanometer":[4],"regime":[5],"is":[6],"becoming":[7],"increasingly":[8],"difficult":[9],"due":[10],"to":[11,21,58,62],"process":[12],"variations.":[13,26,43],"ASIC":[14,77],"designers":[15],"have":[16],"adopted":[17],"statistical":[18],"optimization":[19],"techniques":[20],"mitigate":[22],"effects":[24,41],"of":[25,42,50,53,66,69],"The":[27],"FPGA":[28,75],"community":[29],"on":[30,39,55],"other":[32],"hand,":[33],"has":[34],"only":[35],"recently":[36],"started":[37],"focussing":[38],"This":[44],"paper":[45],"presents":[46],"a":[47,64,82],"comparative":[48],"study":[49],"impact":[52],"variations":[54],"designs":[56],"mapped":[57],"FPGAs":[59],"and":[60,76],"ASICs":[61],"get":[63],"measure":[65],"severity":[68],"problem":[71],"both":[73],"domains.":[78],"We":[79],"also":[80],"propose":[81],"variation":[83],"aware":[84],"router":[85],"that":[86],"reduces":[87],"yield":[89,102],"loss":[90],"by":[91,97],"7.61X,":[92],"or":[93],"circuit":[95],"delay":[96],"3.95%":[98],"for":[99,103],"same":[101],"MCNC":[105],"benchmarks.":[106]},"counts_by_year":[{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}