{"id":"https://openalex.org/W2160573804","doi":"https://doi.org/10.1145/1216919.1216926","title":"A versatile, low latency HyperTransport core","display_name":"A versatile, low latency HyperTransport core","publication_year":2007,"publication_date":"2007-02-18","ids":{"openalex":"https://openalex.org/W2160573804","doi":"https://doi.org/10.1145/1216919.1216926","mag":"2160573804"},"language":"en","primary_location":{"id":"doi:10.1145/1216919.1216926","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1216919.1216926","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024044121","display_name":"David Slogsnat","orcid":null},"institutions":[{"id":"https://openalex.org/I177802217","display_name":"University of Mannheim","ror":"https://ror.org/031bsb921","country_code":"DE","type":"education","lineage":["https://openalex.org/I177802217"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"David Slogsnat","raw_affiliation_strings":["University of Mannheim, Mannheim, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Mannheim, Mannheim, Germany","institution_ids":["https://openalex.org/I177802217"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041545756","display_name":"Alexander Giese","orcid":null},"institutions":[{"id":"https://openalex.org/I177802217","display_name":"University of Mannheim","ror":"https://ror.org/031bsb921","country_code":"DE","type":"education","lineage":["https://openalex.org/I177802217"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Alexander Giese","raw_affiliation_strings":["University of Mannheim, Mannheim, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Mannheim, Mannheim, Germany","institution_ids":["https://openalex.org/I177802217"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024518073","display_name":"Ulrich Br\u00fcning","orcid":null},"institutions":[{"id":"https://openalex.org/I177802217","display_name":"University of Mannheim","ror":"https://ror.org/031bsb921","country_code":"DE","type":"education","lineage":["https://openalex.org/I177802217"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Ulrich Br\u00fcning","raw_affiliation_strings":["University of Mannheim, Mannheim, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Mannheim, Mannheim, Germany","institution_ids":["https://openalex.org/I177802217"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I177802217"],"apc_list":null,"apc_paid":null,"fwci":5.0961,"has_fulltext":false,"cited_by_count":26,"citation_normalized_percentile":{"value":0.95229902,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"45","last_page":"52"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7893756628036499},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7235294580459595},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6703809499740601},{"id":"https://openalex.org/keywords/coprocessor","display_name":"Coprocessor","score":0.5896962881088257},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.49006712436676025},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4715338349342346},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.4626854658126831},{"id":"https://openalex.org/keywords/low-latency","display_name":"Low latency (capital markets)","score":0.43744584918022156},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.42504578828811646},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4196867346763611},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.09761697053909302}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7893756628036499},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7235294580459595},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6703809499740601},{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.5896962881088257},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.49006712436676025},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4715338349342346},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.4626854658126831},{"id":"https://openalex.org/C46637626","wikidata":"https://www.wikidata.org/wiki/Q6693015","display_name":"Low latency (capital markets)","level":2,"score":0.43744584918022156},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.42504578828811646},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4196867346763611},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.09761697053909302},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/1216919.1216926","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1216919.1216926","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.130.8440","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.130.8440","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ra.informatik.uni-mannheim.de/pages/papers/2007/2.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.132.7139","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.132.7139","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.hypertransport.org/docs/wp/uom_core_design.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5299999713897705,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W119823125","https://openalex.org/W1971491113","https://openalex.org/W1977850862","https://openalex.org/W2103764902","https://openalex.org/W2117791917","https://openalex.org/W2133712953","https://openalex.org/W2139093700"],"related_works":["https://openalex.org/W2393701163","https://openalex.org/W4232546846","https://openalex.org/W2011081932","https://openalex.org/W2387382509","https://openalex.org/W2116209852","https://openalex.org/W3205411230","https://openalex.org/W4286899009","https://openalex.org/W9168048","https://openalex.org/W4300849822","https://openalex.org/W4376480820"],"abstract_inverted_index":{"This":[0,35],"paper":[1,55],"presents":[2],"the":[3,29,39,43,73,132,141,145,164],"design":[4,41],"of":[5,60,79,88,112,140,144],"a":[6,17,57,70,76,84,98,107,113,125,149],"generic":[7,40],"HyperTransport":[8,108,147],"(HT)":[9],"core.":[10],"It":[11],"is":[12,63,135,148,167,180],"specially":[13],"optimized":[14],"to":[15,45,138],"achieve":[16],"very":[18,126],"low":[19,128],"latency.":[20],"The":[21,50,91,158,177],"core":[22,74,160,179],"has":[23,94,103],"been":[24,95,104],"verified":[25],"in":[26,53,65,120,161],"system":[27],"using":[28,97],"rapid":[30],"prototyping":[31,172],"methodology":[32],"with":[33,163],"FPGAs.":[34,49],"exhaustive":[36],"verification":[37,93],"and":[38,48,82,174],"allows":[42],"mapping":[44],"both":[46],"ASICs":[47],"implementation":[51],"described":[52],"this":[54],"supports":[56,75],"link":[58,77],"width":[59],"16bit,":[61],"as":[62,131,182],"used":[64],"Opteron":[66,115,121],"based":[67,116,122],"systems.":[68],"On":[69],"Xilinx":[71],"Virtex4FX60,":[72],"frequency":[78],"400MHz":[80],"DDR":[81],"offers":[83],"maximum":[85],"bidirectional":[86],"bandwidth":[87],"3.6":[89],"GB/s.":[90],"in-system":[92],"performed":[96],"custom":[99],"FPGA":[100,175],"board":[101,166],"that":[102],"plugged":[105],"into":[106],"Extension":[109],"Connector":[110],"(HTX)":[111],"standard":[114],"mainboard.":[117],"HTX":[118,133,165],"slots":[119],"mainboards":[123],"allow":[124],"high-bandwidth,":[127],"latency":[129],"communication,":[130],"device":[134],"directly":[136],"connected":[137],"one":[139],"Hyper-Transport":[142],"links":[143],"processor.":[146],"packet-based":[150],"interconnect":[151],"technology":[152],"for":[153,171],"low-latency,":[154],"high-bandwidth":[155],"point-topoint":[156],"connections.":[157],"HT":[159,178],"combination":[162],"an":[168],"ideal":[169],"base":[170],"systems":[173],"coprocessors.":[176],"available":[181],"open":[183],"source.":[184]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}