{"id":"https://openalex.org/W1992572001","doi":"https://doi.org/10.1145/1216544.1216548","title":"Software-directed power-aware interconnection networks","display_name":"Software-directed power-aware interconnection networks","publication_year":2007,"publication_date":"2007-03-01","ids":{"openalex":"https://openalex.org/W1992572001","doi":"https://doi.org/10.1145/1216544.1216548","mag":"1992572001"},"language":"en","primary_location":{"id":"doi:10.1145/1216544.1216548","is_oa":true,"landing_page_url":"https://doi.org/10.1145/1216544.1216548","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/1216544.1216548","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://dl.acm.org/doi/pdf/10.1145/1216544.1216548","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020344922","display_name":"Vassos Soteriou","orcid":"https://orcid.org/0000-0002-2818-0459"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vassos Soteriou","raw_affiliation_strings":["Princeton University, Princeton, New Jersey","Princeton University, Princeton New Jersey"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Princeton University, Princeton, New Jersey","institution_ids":["https://openalex.org/I20089843"]},{"raw_affiliation_string":"Princeton University, Princeton New Jersey","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017210203","display_name":"Noel Eisley","orcid":null},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Noel Eisley","raw_affiliation_strings":["Princeton University, Princeton, New Jersey","Princeton University, Princeton New Jersey"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Princeton University, Princeton, New Jersey","institution_ids":["https://openalex.org/I20089843"]},{"raw_affiliation_string":"Princeton University, Princeton New Jersey","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057413185","display_name":"Li-Shiuan Peh","orcid":"https://orcid.org/0000-0001-9010-6519"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Li-Shiuan Peh","raw_affiliation_strings":["Princeton University, Princeton, New Jersey","Princeton University, Princeton New Jersey"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Princeton University, Princeton, New Jersey","institution_ids":["https://openalex.org/I20089843"]},{"raw_affiliation_string":"Princeton University, Princeton New Jersey","institution_ids":["https://openalex.org/I20089843"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I20089843"],"apc_list":null,"apc_paid":null,"fwci":3.3239,"has_fulltext":true,"cited_by_count":38,"citation_normalized_percentile":{"value":0.92356228,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"4","issue":"1","first_page":"5","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8672080636024475},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.6371158957481384},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6200032234191895},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5651534199714661},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5644823312759399},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5323745608329773},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4256702661514282},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.37966427206993103},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.37956276535987854},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.26350241899490356},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.19664400815963745},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.19023874402046204}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8672080636024475},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.6371158957481384},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6200032234191895},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5651534199714661},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5644823312759399},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5323745608329773},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4256702661514282},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.37966427206993103},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.37956276535987854},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.26350241899490356},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.19664400815963745},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.19023874402046204}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1216544.1216548","is_oa":true,"landing_page_url":"https://doi.org/10.1145/1216544.1216548","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/1216544.1216548","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1145/1216544.1216548","is_oa":true,"landing_page_url":"https://doi.org/10.1145/1216544.1216548","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/1216544.1216548","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.6100000143051147}],"awards":[{"id":"https://openalex.org/G1816167823","display_name":"ITR:     Collaborative Research:     A Multi-Level Approach to Power-Efficient Opto-Electronic Interconnection Networks","funder_award_id":"0324891","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G5917309213","display_name":"CAREER:    Self-Regulating Power-Aware Interconnection Networks","funder_award_id":"0237540","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G6671297155","display_name":null,"funder_award_id":"CAREER","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G8744378809","display_name":"NGS:Collaborative Proposal:Structural and Composable Performance Simulation of Complex Systems","funder_award_id":"0305617","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320309292","display_name":"Princeton University","ror":"https://ror.org/00hx57361"},{"id":"https://openalex.org/F4320310620","display_name":"University of Texas at Austin","ror":"https://ror.org/00hj54h04"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W1992572001.pdf","grobid_xml":"https://content.openalex.org/works/W1992572001.grobid-xml"},"referenced_works_count":44,"referenced_works":["https://openalex.org/W114148695","https://openalex.org/W156825290","https://openalex.org/W1531981541","https://openalex.org/W1862469596","https://openalex.org/W1973468635","https://openalex.org/W1987095420","https://openalex.org/W2026192802","https://openalex.org/W2038198320","https://openalex.org/W2043276498","https://openalex.org/W2057920389","https://openalex.org/W2085583524","https://openalex.org/W2101695800","https://openalex.org/W2102387714","https://openalex.org/W2108783911","https://openalex.org/W2109259551","https://openalex.org/W2110552224","https://openalex.org/W2113700934","https://openalex.org/W2117285153","https://openalex.org/W2120326208","https://openalex.org/W2122416961","https://openalex.org/W2123184444","https://openalex.org/W2126495708","https://openalex.org/W2129442721","https://openalex.org/W2129959195","https://openalex.org/W2136138043","https://openalex.org/W2139041897","https://openalex.org/W2142455831","https://openalex.org/W2145021036","https://openalex.org/W2147801838","https://openalex.org/W2149130672","https://openalex.org/W2150007533","https://openalex.org/W2154628372","https://openalex.org/W2156475585","https://openalex.org/W2157373341","https://openalex.org/W2167157104","https://openalex.org/W2167523594","https://openalex.org/W2171215895","https://openalex.org/W2913252637","https://openalex.org/W2913899326","https://openalex.org/W4232580036","https://openalex.org/W4242368470","https://openalex.org/W4249962740","https://openalex.org/W4253795537","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W3096456556","https://openalex.org/W4240253816","https://openalex.org/W2169584677","https://openalex.org/W2979513934","https://openalex.org/W2264746079","https://openalex.org/W2889526943","https://openalex.org/W2007651078","https://openalex.org/W1987160526","https://openalex.org/W121182129","https://openalex.org/W91363257"],"abstract_inverted_index":{"Interconnection":[0],"networks":[1],"have":[2,35,53],"been":[3],"deployed":[4],"as":[5,149],"the":[6,70,92,110,114,126,130,135,147,164,202,221],"communication":[7,48,116,208],"fabric":[8],"in":[9,59,69,152,155,194,227,243,320],"a":[10,37,65,224,239,317,328],"wide":[11],"spectrum":[12],"of":[13,40,72,85,223,330],"parallel":[14,89,293],"computer":[15],"systems,":[16,245,294],"ranging":[17,295,322],"from":[18,143,296,323],"chip":[19,41],"multiprocessors":[20],"(CMPs)":[21],"and":[22,29,46,87,134,260,278],"embedded":[23],"multicore":[24],"systems-on-a-chip":[25],"(SoCs)":[26],"to":[27,56,81,125,146,229,256,284,300,314,325],"clusters":[28],"server":[30],"blades.":[31],"Recent":[32],"technology":[33],"trends":[34,52],"permitted":[36],"rapid":[38],"growth":[39],"resources,":[42],"faster":[43],"clock":[44],"rates,":[45],"wider":[47],"bandwidths,":[49],"however,":[50],"these":[51,119,244,280],"also":[54],"led":[55],"an":[57,180,270],"increase":[58,319],"power":[60,111,132,233,241,264,307],"consumption":[61,308],"that":[62,105,176,219,305],"is":[63,193],"becoming":[64],"key":[66],"limiting":[67],"factor":[68],"design":[71],"such":[73],"scalable":[74],"interconnected":[75],"systems.":[76,90],"Power-aware":[77],"networks,":[78],"therefore,":[79],"need":[80],"become":[82],"inherent":[83],"components":[84],"single":[86],"multi-chip":[88,302],"In":[91,163,197],"hardware":[93,183,272],"arena,":[94,166],"recent":[95],"interconnection":[96],"network":[97,115,139,158,232,237,275,286],"power-management":[98],"research":[99,168,188],"work":[100],"has":[101,172],"employed":[102],"limited-scope":[103,120],"techniques":[104,121,218],"mostly":[106],"focus":[107],"on":[108,129,138,169],"reducing":[109],"consumed":[112],"by":[113,312],"links.":[117],"As":[118],"are":[122],"not":[123],"tailored":[124],"applications":[127],"running":[128],"network,":[131],"savings":[133,265],"corresponding":[136],"impact":[137],"latency":[140],"vary":[141],"significantly":[142],"one":[144],"application":[145,181,267],"next":[148],"we":[150,200],"demonstrate":[151],"this":[153,198],"paper;":[154],"many":[156],"cases,":[157],"performance":[159],"can":[160,177,309],"severely":[161],"suffer.":[162],"software":[165,217],"extensive":[167],"compile-time":[170],"optimizations":[171],"produced":[173],"parallelizing":[174,191,225],"compilers":[175,192],"efficiently":[178],"map":[179],"onto":[182],"for":[184,212,263],"high":[185],"performance.":[186,287],"However,":[187],"into":[189],"power-aware":[190],"its":[195],"infancy.":[196],"paper,":[199],"take":[201],"first":[203],"steps":[204],"toward":[205],"tailoring":[206],"applications'":[207],"needs":[209],"at":[210],"run-time":[211,231],"low":[213],"power.":[214],"We":[215,235],"propose":[216],"extend":[220],"flow":[222],"compiler":[226],"order":[228],"direct":[230],"reduction.":[234],"target":[236],"links,":[238],"significant":[240],"consumer":[242],"allowing":[246],"dynamic":[247],"voltage":[248,259],"scaling":[249],"(DVS)":[250],"instructions":[251],"extracted":[252],"during":[253,266],"static":[254],"compilation":[255],"orchestrate":[257],"link":[258,306],"frequency":[261],"transitions":[262],"run-time.":[268],"Concurrently,":[269],"online":[271],"mechanism":[273],"measures":[274],"congestion":[276],"levels":[277],"adapts":[279],"off-line":[281],"DVS":[282],"settings":[283],"maximize":[285],"Our":[288],"simulations":[289],"over":[290],"three":[291],"existing":[292],"very":[297],"fine-grained":[298],"single-chip":[299],"coarse-grained":[301],"architectures,":[303],"show":[304],"be":[310],"reduced":[311],"up":[313],"76.3%,":[315],"with":[316],"minor":[318],"latency,":[321],"0.18":[324],"6.78%":[326],"across":[327],"number":[329],"benchmark":[331],"suites.":[332]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":5},{"year":2013,"cited_by_count":5},{"year":2012,"cited_by_count":7}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}
