{"id":"https://openalex.org/W2041653803","doi":"https://doi.org/10.1145/1183401.1183428","title":"Design space exploration for multicore architectures","display_name":"Design space exploration for multicore architectures","publication_year":2006,"publication_date":"2006-06-28","ids":{"openalex":"https://openalex.org/W2041653803","doi":"https://doi.org/10.1145/1183401.1183428","mag":"2041653803"},"language":"en","primary_location":{"id":"doi:10.1145/1183401.1183428","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1183401.1183428","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 20th annual international conference on Supercomputing","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038294114","display_name":"Matteo Monchiero","orcid":null},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Matteo Monchiero","raw_affiliation_strings":["Politecnico di Milano, Via Ponzio, Milano, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Via Ponzio, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036543571","display_name":"Ram\u00f3n Canal","orcid":"https://orcid.org/0000-0003-4542-204X"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Ramon Canal","raw_affiliation_strings":["Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100733331","display_name":"Antonio Gonz\u00e1lez","orcid":"https://orcid.org/0000-0002-0009-0996"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Antonio Gonz\u00e1lez","raw_affiliation_strings":["Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain and Intel Labs-Universitat, Barcelona, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain and Intel Labs-Universitat, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":5.1332,"has_fulltext":false,"cited_by_count":87,"citation_normalized_percentile":{"value":0.96242133,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"177","last_page":"186"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.7843176126480103},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7782840132713318},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.7260924577713013},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5685297250747681},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.5581251978874207},{"id":"https://openalex.org/keywords/reuse","display_name":"Reuse","score":0.5236411094665527},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5023465156555176},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.49682000279426575},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4800375699996948},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.4781390428543091},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4622634947299957},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4511326253414154},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42418742179870605},{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.421924889087677},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.42154204845428467},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.41996362805366516}],"concepts":[{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.7843176126480103},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7782840132713318},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.7260924577713013},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5685297250747681},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.5581251978874207},{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.5236411094665527},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5023465156555176},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.49682000279426575},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4800375699996948},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.4781390428543091},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4622634947299957},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4511326253414154},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42418742179870605},{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.421924889087677},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.42154204845428467},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.41996362805366516},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1183401.1183428","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1183401.1183428","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 20th annual international conference on Supercomputing","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1598283091","https://openalex.org/W1987215594","https://openalex.org/W2022740893","https://openalex.org/W2052839611","https://openalex.org/W2087645421","https://openalex.org/W2101360724","https://openalex.org/W2102387714","https://openalex.org/W2102727118","https://openalex.org/W2105834362","https://openalex.org/W2117738267","https://openalex.org/W2120368896","https://openalex.org/W2134131177","https://openalex.org/W2137675939","https://openalex.org/W2138351227","https://openalex.org/W2141923369","https://openalex.org/W2145021036","https://openalex.org/W2145252892","https://openalex.org/W2145871983","https://openalex.org/W2148954445","https://openalex.org/W2150121003","https://openalex.org/W2150392806","https://openalex.org/W2152165066","https://openalex.org/W2161864047","https://openalex.org/W2164813835","https://openalex.org/W4244034697"],"related_works":["https://openalex.org/W2138401961","https://openalex.org/W2144917103","https://openalex.org/W4388721364","https://openalex.org/W2133803564","https://openalex.org/W1985714852","https://openalex.org/W4308092838","https://openalex.org/W2942050196","https://openalex.org/W1953929790","https://openalex.org/W4249576260","https://openalex.org/W2129188682"],"abstract_inverted_index":{"Multicore":[0],"architectures":[1],"are":[2,120,141],"ruling":[3],"the":[4,88,93,104,107,123,126,146,153,158],"recent":[5],"microprocessor":[6],"design":[7,89,129,160],"trend.":[8],"This":[9],"is":[10,58],"due":[11],"to":[12,92,112,156],"different":[13,108],"reasons:":[14],"better":[15,26],"performance,":[16,113],"thread-level":[17],"parallelism":[18],"bounds":[19],"in":[20],"modern":[21],"applications,":[22],"ILP":[23],"diminishing":[24],"returns,":[25],"thermal/power":[27],"scaling":[28],"(many":[29],"small":[30],"cores":[31],"dissipate":[32],"less":[33],"than":[34],"a":[35,48,61,66,76],"large":[36],"and":[37,42,73,75,100,116,128,143],"complex":[38],"one);":[39],"and,":[40],"ease":[41],"reuse":[43],"of":[44,51,60,64,70,95,106,125,148],"design.This":[45],"paper":[46],"presents":[47],"thorough":[49],"evaluation":[50],"multicore":[52],"architectures.":[53],"The":[54],"architecture":[55],"we":[56,133],"target":[57],"composed":[59],"configurable":[62],"number":[63,94],"cores,":[65,96],"memory":[67,84],"hierarchy":[68],"consisting":[69],"private":[71],"L1":[72],"L2,":[74],"shared":[77,83],"bus":[78],"interconnect.":[79],"We":[80,86],"consider":[81],"parallel":[82],"applications.":[85],"explore":[87],"space":[90],"related":[91],"L2":[97],"cache":[98],"size":[99],"processor":[101],"complexity,":[102],"showing":[103],"behavior":[105],"configurations/applications":[109],"with":[110],"respect":[111],"energy":[114],"consumption":[115],"temperature.":[117],"Design":[118],"tradeoffs":[119],"analyzed,":[121],"stressing":[122],"interdependency":[124],"metrics":[127],"factors.":[130],"In":[131],"particular,":[132],"evaluate":[134],"several":[135],"chip":[136],"floorplans.":[137],"Their":[138],"power/thermal":[139],"characteristics":[140],"analyzed":[142],"they":[144],"show":[145],"importance":[147],"considering":[149],"thermal":[150],"effects":[151],"at":[152],"architectural":[154],"level":[155],"achieve":[157],"best":[159],"choice.":[161]},"counts_by_year":[{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":6},{"year":2015,"cited_by_count":11},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":11},{"year":2012,"cited_by_count":12}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
