{"id":"https://openalex.org/W1989165865","doi":"https://doi.org/10.1145/1176760.1176774","title":"FlashCache","display_name":"FlashCache","publication_year":2006,"publication_date":"2006-10-22","ids":{"openalex":"https://openalex.org/W1989165865","doi":"https://doi.org/10.1145/1176760.1176774","mag":"1989165865"},"language":"en","primary_location":{"id":"doi:10.1145/1176760.1176774","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1176760.1176774","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035195018","display_name":"Taeho Kgil","orcid":null},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan\u2013Ann Arbor","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Taeho Kgil","raw_affiliation_strings":["The University of Michigan, Ann Arbor, USA","the University of Michigan, Ann Arbor, USA"],"affiliations":[{"raw_affiliation_string":"The University of Michigan, Ann Arbor, USA","institution_ids":["https://openalex.org/I27837315"]},{"raw_affiliation_string":"the University of Michigan, Ann Arbor, USA","institution_ids":["https://openalex.org/I27837315"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037541525","display_name":"Trevor Mudge","orcid":"https://orcid.org/0000-0001-7845-2187"},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan\u2013Ann Arbor","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Trevor Mudge","raw_affiliation_strings":["The University of Michigan, Ann Arbor, USA","the University of Michigan, Ann Arbor, USA"],"affiliations":[{"raw_affiliation_string":"The University of Michigan, Ann Arbor, USA","institution_ids":["https://openalex.org/I27837315"]},{"raw_affiliation_string":"the University of Michigan, Ann Arbor, USA","institution_ids":["https://openalex.org/I27837315"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5035195018"],"corresponding_institution_ids":["https://openalex.org/I27837315"],"apc_list":null,"apc_paid":null,"fwci":7.2428,"has_fulltext":false,"cited_by_count":123,"citation_normalized_percentile":{"value":0.97237521,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"103","last_page":"112"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10101","display_name":"Cloud Computing and Resource Management","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8317848443984985},{"id":"https://openalex.org/keywords/write-buffer","display_name":"Write buffer","score":0.6940599083900452},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.6583709120750427},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6017981171607971},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.5961119532585144},{"id":"https://openalex.org/keywords/page-cache","display_name":"Page cache","score":0.5889554023742676},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.5764774680137634},{"id":"https://openalex.org/keywords/flash-file-system","display_name":"Flash file system","score":0.5227958559989929},{"id":"https://openalex.org/keywords/disk-buffer","display_name":"Disk buffer","score":0.4872259199619293},{"id":"https://openalex.org/keywords/server","display_name":"Server","score":0.47335052490234375},{"id":"https://openalex.org/keywords/flash","display_name":"Flash (photography)","score":0.4429381489753723},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42832309007644653},{"id":"https://openalex.org/keywords/idle","display_name":"Idle","score":0.41930216550827026},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.41223227977752686},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3743586242198944},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.33813947439193726},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.33526283502578735},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.3010557293891907},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.23852959275245667},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.23631274700164795},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.22800776362419128},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.2273329794406891},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.22695443034172058}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8317848443984985},{"id":"https://openalex.org/C89089495","wikidata":"https://www.wikidata.org/wiki/Q8038418","display_name":"Write buffer","level":5,"score":0.6940599083900452},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.6583709120750427},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6017981171607971},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.5961119532585144},{"id":"https://openalex.org/C36340418","wikidata":"https://www.wikidata.org/wiki/Q7124288","display_name":"Page cache","level":5,"score":0.5889554023742676},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.5764774680137634},{"id":"https://openalex.org/C27670709","wikidata":"https://www.wikidata.org/wiki/Q5457555","display_name":"Flash file system","level":4,"score":0.5227958559989929},{"id":"https://openalex.org/C202623185","wikidata":"https://www.wikidata.org/wiki/Q375176","display_name":"Disk buffer","level":3,"score":0.4872259199619293},{"id":"https://openalex.org/C93996380","wikidata":"https://www.wikidata.org/wiki/Q44127","display_name":"Server","level":2,"score":0.47335052490234375},{"id":"https://openalex.org/C2777526259","wikidata":"https://www.wikidata.org/wiki/Q221836","display_name":"Flash (photography)","level":2,"score":0.4429381489753723},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42832309007644653},{"id":"https://openalex.org/C16320812","wikidata":"https://www.wikidata.org/wiki/Q1812200","display_name":"Idle","level":2,"score":0.41930216550827026},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.41223227977752686},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3743586242198944},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.33813947439193726},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33526283502578735},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.3010557293891907},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.23852959275245667},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.23631274700164795},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.22800776362419128},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.2273329794406891},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.22695443034172058},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1176760.1176774","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1176760.1176774","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W35641434","https://openalex.org/W1743133773","https://openalex.org/W2022740893","https://openalex.org/W2023211675","https://openalex.org/W2044206819","https://openalex.org/W2100384468","https://openalex.org/W2119830064","https://openalex.org/W2120912800","https://openalex.org/W2124799219","https://openalex.org/W2133985894","https://openalex.org/W2729704222","https://openalex.org/W4236312724"],"related_works":["https://openalex.org/W2398854546","https://openalex.org/W2401672171","https://openalex.org/W2186187728","https://openalex.org/W2117595384","https://openalex.org/W2165959208","https://openalex.org/W2166109463","https://openalex.org/W2488182804","https://openalex.org/W1916340650","https://openalex.org/W2295267406","https://openalex.org/W4294408872"],"abstract_inverted_index":{"We":[0],"propose":[1,124],"an":[2],"architecture":[3,19,55],"that":[4,101,122],"uses":[5,20],"NAND":[6],"flash":[7,42,73,106],"memory":[8,12,43],"to":[9,49,99],"reduce":[10],"main":[11],"power":[13,62,82],"in":[14,94],"web":[15,95],"server":[16],"platforms.":[17],"Our":[18],"a":[21,29,35,41,50,69],"two":[22],"level":[23],"file":[24,37,45],"buffer":[25,38,46],"cache":[26],"composed":[27],"of":[28,58,71,78,105],"relatively":[30],"small":[31],"DRAM,":[32],"which":[33,75],"includes":[34],"primary":[36,103],"cache,":[39],"and":[40,85,108],"secondary":[44],"cache.":[47],"Compared":[48],"conventional":[51],"DRAM-only":[52],"architecture,":[53],"our":[54],"consumes":[56,76],"orders":[57,77],"magnitude":[59,79],"less":[60,80],"idle":[61,81],"while":[63],"remaining":[64],"cost":[65],"effective.":[66],"This":[67],"is":[68,86],"result":[70],"using":[72],"memory,":[74],"than":[83],"DRAM":[84],"twice":[87],"as":[88],"dense.":[89],"The":[90],"client":[91],"request":[92],"behavior":[93],"servers,":[96],"allows":[97],"us":[98],"show":[100],"the":[102,117],"drawbacks":[104],"memory?endurance":[107],"long":[109],"write":[110],"latencies?can":[111],"easily":[112],"be":[113],"overcome.":[114],"In":[115],"fact":[116],"wear-level":[118],"aware":[119],"management":[120],"techniques":[121],"we":[123],"are":[125],"not":[126],"heavily":[127],"used.":[128]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":8},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":10},{"year":2015,"cited_by_count":13},{"year":2014,"cited_by_count":11},{"year":2013,"cited_by_count":13},{"year":2012,"cited_by_count":10}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2016-06-24T00:00:00"}