{"id":"https://openalex.org/W2155040834","doi":"https://doi.org/10.1145/1176760.1176769","title":"Modeling heterogeneous SoCs with SystemC","display_name":"Modeling heterogeneous SoCs with SystemC","publication_year":2006,"publication_date":"2006-10-22","ids":{"openalex":"https://openalex.org/W2155040834","doi":"https://doi.org/10.1145/1176760.1176769","mag":"2155040834"},"language":"en","primary_location":{"id":"doi:10.1145/1176760.1176769","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1176760.1176769","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031873224","display_name":"Ankush Varma","orcid":null},"institutions":[{"id":"https://openalex.org/I1321296531","display_name":"National Institute of Standards and Technology","ror":"https://ror.org/05xpvk416","country_code":"US","type":"funder","lineage":["https://openalex.org/I1321296531","https://openalex.org/I1343035065"]},{"id":"https://openalex.org/I66946132","display_name":"University of Maryland, College Park","ror":"https://ror.org/047s2c258","country_code":"US","type":"education","lineage":["https://openalex.org/I66946132"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ankush Varma","raw_affiliation_strings":["University of Maryland, College Park, MD and National Institute of Standards and Technology (NIST), Gaithersburg, MD"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Maryland, College Park, MD and National Institute of Standards and Technology (NIST), Gaithersburg, MD","institution_ids":["https://openalex.org/I1321296531","https://openalex.org/I66946132"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110198902","display_name":"Muhammad Y. Afridi","orcid":null},"institutions":[{"id":"https://openalex.org/I1321296531","display_name":"National Institute of Standards and Technology","ror":"https://ror.org/05xpvk416","country_code":"US","type":"funder","lineage":["https://openalex.org/I1321296531","https://openalex.org/I1343035065"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Yaqub Afridi","raw_affiliation_strings":["National Institute of Standards and Technology (NIST), Gaithersburg, MD"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Institute of Standards and Technology (NIST), Gaithersburg, MD","institution_ids":["https://openalex.org/I1321296531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075864803","display_name":"Akin Akturk","orcid":"https://orcid.org/0000-0002-6409-3221"},"institutions":[{"id":"https://openalex.org/I66946132","display_name":"University of Maryland, College Park","ror":"https://ror.org/047s2c258","country_code":"US","type":"education","lineage":["https://openalex.org/I66946132"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Akin Akturk","raw_affiliation_strings":["University of Maryland, College Park, MD"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Maryland, College Park, MD","institution_ids":["https://openalex.org/I66946132"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043466976","display_name":"Paul Klein","orcid":"https://orcid.org/0000-0002-0141-3902"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Paul Klein","raw_affiliation_strings":["Intel Corporation, Chandler, AZ"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Chandler, AZ","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052627846","display_name":"Allen R. Hefner","orcid":null},"institutions":[{"id":"https://openalex.org/I1321296531","display_name":"National Institute of Standards and Technology","ror":"https://ror.org/05xpvk416","country_code":"US","type":"funder","lineage":["https://openalex.org/I1321296531","https://openalex.org/I1343035065"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Allen R. Hefner","raw_affiliation_strings":["National Institute of Standards and Technology (NIST), Gaithersburg, MD"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Institute of Standards and Technology (NIST), Gaithersburg, MD","institution_ids":["https://openalex.org/I1321296531"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5047597896","display_name":"Bruce Jacob","orcid":"https://orcid.org/0009-0005-3493-8245"},"institutions":[{"id":"https://openalex.org/I66946132","display_name":"University of Maryland, College Park","ror":"https://ror.org/047s2c258","country_code":"US","type":"education","lineage":["https://openalex.org/I66946132"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Bruce Jacob","raw_affiliation_strings":["University of Maryland, College Park, MD"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Maryland, College Park, MD","institution_ids":["https://openalex.org/I66946132"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"54","last_page":"64"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.9900364875793457},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7423593401908875},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.6605909466743469},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6581010818481445},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6399760246276855},{"id":"https://openalex.org/keywords/transaction-level-modeling","display_name":"Transaction-level modeling","score":0.5892617106437683},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.550740659236908},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.5467925071716309},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5179928541183472},{"id":"https://openalex.org/keywords/microelectromechanical-systems","display_name":"Microelectromechanical systems","score":0.4772186875343323},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.47673499584198},{"id":"https://openalex.org/keywords/systems-design","display_name":"Systems design","score":0.4387408196926117},{"id":"https://openalex.org/keywords/systems-modeling","display_name":"Systems modeling","score":0.4172012209892273},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.13507768511772156},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09004321694374084}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.9900364875793457},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7423593401908875},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.6605909466743469},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6581010818481445},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6399760246276855},{"id":"https://openalex.org/C169571997","wikidata":"https://www.wikidata.org/wiki/Q966099","display_name":"Transaction-level modeling","level":3,"score":0.5892617106437683},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.550740659236908},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.5467925071716309},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5179928541183472},{"id":"https://openalex.org/C37977207","wikidata":"https://www.wikidata.org/wiki/Q175561","display_name":"Microelectromechanical systems","level":2,"score":0.4772186875343323},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.47673499584198},{"id":"https://openalex.org/C31352089","wikidata":"https://www.wikidata.org/wiki/Q3750474","display_name":"Systems design","level":2,"score":0.4387408196926117},{"id":"https://openalex.org/C110963975","wikidata":"https://www.wikidata.org/wiki/Q12070446","display_name":"Systems modeling","level":2,"score":0.4172012209892273},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.13507768511772156},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09004321694374084},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1176760.1176769","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1176760.1176769","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1604550703","https://openalex.org/W1758799934","https://openalex.org/W1788602313","https://openalex.org/W1972135346","https://openalex.org/W2036817382","https://openalex.org/W2100895126","https://openalex.org/W2126173506","https://openalex.org/W2134154233","https://openalex.org/W2135146850","https://openalex.org/W2138803629","https://openalex.org/W2145742417","https://openalex.org/W2148740615","https://openalex.org/W2151174323","https://openalex.org/W2165059292","https://openalex.org/W2172185362","https://openalex.org/W2182860675","https://openalex.org/W2952721922"],"related_works":["https://openalex.org/W1525398417","https://openalex.org/W2069603759","https://openalex.org/W2533881872","https://openalex.org/W2170029576","https://openalex.org/W2266880325","https://openalex.org/W2548514518","https://openalex.org/W2790192245","https://openalex.org/W1996984607","https://openalex.org/W2059569687","https://openalex.org/W2537443402"],"abstract_inverted_index":{"Designers":[0],"of":[1,28,65,68,86,123,130,141,144],"SoCs":[2],"with":[3],"non-digital":[4,70],"components,":[5],"such":[6,19,177],"as":[7,20],"analog":[8],"or":[9],"MEMS":[10,73,95,131,159],"devices,":[11],"can":[12,163,174],"currently":[13],"use":[14],"high-level":[15],"system":[16,42,52,108],"design":[17,43,46,109,161,188],"languages,":[18],"SystemC,":[21,135],"to":[22,39,79,99,147,181],"model":[23],"only":[24],"the":[25,94,119,127,142,187],"digital":[26],"parts":[27],"a":[29,33,66,83,87,100,124,137,148],"system.":[30,150],"This":[31,59,91],"is":[32],"significant":[34],"limitation,":[35],"making":[36],"it":[37,168],"difficult":[38],"perform":[40],"key":[41],"tasks":[44],"--":[45,54,72,75],"space":[47],"exploration,":[48],"hardware-software":[49],"co-design":[50],"and":[51,76,110,136,179],"verification":[53],"at":[55,103],"an":[56],"early":[57,185],"stage.":[58],"paper":[60],"describes":[61,170],"lumped":[62],"analytical":[63],"models":[64,122],"class":[67],"complex":[69],"devices":[71],"microhotplates":[74],"presents":[77],"techniques":[78,146],"integrate":[80],"them":[81],"into":[82,157],"SystemC":[84,121],"simulation":[85,102],"heterogeneous":[88],"System-on-a-Chip":[89],"(SoC).":[90],"approach":[92],"makes":[93],"component":[96],"behavior":[97,133],"visible":[98],"full-system":[101,172],"higher":[104],"levels,":[105],"enabling":[106],"realistic":[107],"testing.":[111],"The":[112],"contributions":[113],"made":[114],"in":[115,134,186],"this":[116,153],"work":[117,154],"include":[118],"first":[120,128],"MEMS-based":[125],"SoC,":[126],"modeling":[129,173],"thermal":[132],"detailed":[138],"case":[139],"study":[140],"application":[143],"these":[145],"real":[149],"In":[151],"addition,":[152],"provides":[155],"insights":[156],"how":[158,171],"device-level":[160],"decisions":[162],"significantly":[164],"impact":[165],"system-level":[166],"behavior;":[167],"also":[169],"help":[175,180],"detect":[176],"phenomena":[178],"address":[182],"detected":[183],"problems":[184],"flow.":[189]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
