{"id":"https://openalex.org/W2104862920","doi":"https://doi.org/10.1145/1176254.1176288","title":"Layout aware design of mesh based NoC architectures","display_name":"Layout aware design of mesh based NoC architectures","publication_year":2006,"publication_date":"2006-10-22","ids":{"openalex":"https://openalex.org/W2104862920","doi":"https://doi.org/10.1145/1176254.1176288","mag":"2104862920"},"language":"en","primary_location":{"id":"doi:10.1145/1176254.1176288","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1176254.1176288","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 4th international conference on Hardware/software codesign and system synthesis","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103954792","display_name":"Krishnan Srinivasan","orcid":null},"institutions":[{"id":"https://openalex.org/I55732556","display_name":"Arizona State University","ror":"https://ror.org/03efmqc40","country_code":"US","type":"education","lineage":["https://openalex.org/I55732556"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Krishnan Srinivasan","raw_affiliation_strings":["Arizona State University, Tempe, AZ"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Arizona State University, Tempe, AZ","institution_ids":["https://openalex.org/I55732556"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109416106","display_name":"Karam S. Chatha","orcid":null},"institutions":[{"id":"https://openalex.org/I55732556","display_name":"Arizona State University","ror":"https://ror.org/03efmqc40","country_code":"US","type":"education","lineage":["https://openalex.org/I55732556"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Karam S. Chatha","raw_affiliation_strings":["Arizona State University, Tempe, AZ"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Arizona State University, Tempe, AZ","institution_ids":["https://openalex.org/I55732556"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I55732556"],"apc_list":null,"apc_paid":null,"fwci":0.7051,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":{"value":0.66629205,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"136","last_page":"141"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9925000071525574,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9923999905586243,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.959550142288208},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6690316796302795},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6306620240211487},{"id":"https://openalex.org/keywords/mesh-networking","display_name":"Mesh networking","score":0.6025189161300659},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.5934470891952515},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.5031537413597107},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.48932498693466187},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.46858781576156616},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.461981862783432},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4304606318473816},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4271829426288605},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.40316569805145264},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3703152537345886},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19587454199790955}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.959550142288208},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6690316796302795},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6306620240211487},{"id":"https://openalex.org/C123691950","wikidata":"https://www.wikidata.org/wiki/Q25552104","display_name":"Mesh networking","level":3,"score":0.6025189161300659},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.5934470891952515},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.5031537413597107},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.48932498693466187},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.46858781576156616},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.461981862783432},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4304606318473816},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4271829426288605},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.40316569805145264},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3703152537345886},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19587454199790955},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/1176254.1176288","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1176254.1176288","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 4th international conference on Hardware/software codesign and system synthesis","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.333.2453","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.333.2453","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cecs.uci.edu/~papers/esweek06/codes/p136.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.461.4982","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.461.4982","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://csrl.asu.edu/publications/layoutaware_codes_isss06.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8999999761581421,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1481733864","https://openalex.org/W1974843053","https://openalex.org/W2054302810","https://openalex.org/W2097036543","https://openalex.org/W2114772983","https://openalex.org/W2123184444","https://openalex.org/W2130610076","https://openalex.org/W2145336644","https://openalex.org/W2148439886","https://openalex.org/W2153625096","https://openalex.org/W2156475585","https://openalex.org/W2158734177","https://openalex.org/W2160642395","https://openalex.org/W2160847478","https://openalex.org/W2171940713","https://openalex.org/W6683652925"],"related_works":["https://openalex.org/W1973645408","https://openalex.org/W4236118171","https://openalex.org/W4245901115","https://openalex.org/W2038155649","https://openalex.org/W3036411830","https://openalex.org/W2104862920","https://openalex.org/W2121335669","https://openalex.org/W2388040150","https://openalex.org/W4230718388","https://openalex.org/W2135981148"],"abstract_inverted_index":{"Design":[0],"of":[1,11,19,42,51,63,104,112,128],"System-on-Chip":[2],"(SoC)":[3],"with":[4,125],"regular":[5],"mesh":[6,121],"based":[7,122],"Network-on-Chip":[8],"(NoC)":[9],"consists":[10],"mapping":[12],"processing":[13],"cores":[14],"to":[15,46,99,133],"routers,":[16],"and":[17,32,145],"routing":[18],"the":[20,24,40,43,47,52,61,64,89,105,120,129],"traffic":[21],"traces":[22],"on":[23,60],"topology":[25],"such":[26],"that":[27,84,118],"power":[28,45,49,56,143,149],"consumption":[29,50,57,144],"is":[30,58,108],"minimized,":[31],"performance":[33],"constraints":[34],"are":[35],"satisfied.":[36],"Technology":[37],"scaling":[38],"increases":[39],"contribution":[41,67],"link":[44,55,148],"overall":[48],"NoC.":[53],"Since":[54],"dependent":[59],"length":[62],"link,":[65],"its":[66],"cannot":[68],"be":[69],"accurately":[70],"estimated":[71],"without":[72],"system-level":[73,86],"floorplanning.":[74],"In":[75,131],"this":[76],"paper,":[77],"we":[78],"propose":[79],"a":[80,113],"novel":[81,114],"design":[82,91],"technique":[83,94,138],"integrates":[85],"floorplanning":[87],"into":[88],"NoC":[90,123],"flow.":[92],"Our":[93],"invokes":[95],"an":[96,101,134],"existing":[97,135],"floorplanner":[98],"generate":[100],"initial":[102],"layout":[103],"cores.":[106],"This":[107],"followed":[109],"by":[110],"invocation":[111],"low":[115],"complexity":[116],"algorithm":[117],"generates":[119],"architecture":[124],"complete":[126],"information":[127],"floorplan.":[130],"comparison":[132],"approach,":[136],"our":[137],"results":[139],"in":[140],"lower":[141,147],"total":[142],"much":[146],"consumption.":[150]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
