{"id":"https://openalex.org/W1984890273","doi":"https://doi.org/10.1145/1165573.1165661","title":"Sub-threshold design","display_name":"Sub-threshold design","publication_year":2006,"publication_date":"2006-01-01","ids":{"openalex":"https://openalex.org/W1984890273","doi":"https://doi.org/10.1145/1165573.1165661","mag":"1984890273"},"language":"en","primary_location":{"id":"doi:10.1145/1165573.1165661","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1165573.1165661","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2006 international symposium on Low power electronics and design - ISLPED '06","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5080557997","display_name":"Benton H. Calhoun","orcid":"https://orcid.org/0000-0002-3770-5050"},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"B. H. Calhoun","raw_affiliation_strings":["Virginia, University, Charlottesville, Va"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Virginia, University, Charlottesville, Va","institution_ids":["https://openalex.org/I51556381"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014997096","display_name":"A. Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Wang","raw_affiliation_strings":["Texas Instruments"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas Instruments","institution_ids":["https://openalex.org/I74760111"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101645607","display_name":"Naveen Verma","orcid":"https://orcid.org/0000-0002-8208-5030"},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"N. Verma","raw_affiliation_strings":["Massachussetts Institute of Technology"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Massachussetts Institute of Technology","institution_ids":["https://openalex.org/I63966007"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084128470","display_name":"Anantha P. Chandrakasan","orcid":"https://orcid.org/0000-0002-5977-2748"},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Chandrakasan","raw_affiliation_strings":["Massachussetts Institute of Technology"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Massachussetts Institute of Technology","institution_ids":["https://openalex.org/I63966007"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":84,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"366","last_page":"366"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9950000047683716,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9922000169754028,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.6880338191986084},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6252336502075195},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44568219780921936},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4433857798576355},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.4158353805541992},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34377920627593994},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.23383721709251404},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21131905913352966},{"id":"https://openalex.org/keywords/computer-security","display_name":"Computer security","score":0.10565769672393799}],"concepts":[{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.6880338191986084},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6252336502075195},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44568219780921936},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4433857798576355},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4158353805541992},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34377920627593994},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.23383721709251404},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21131905913352966},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.10565769672393799}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1165573.1165661","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1165573.1165661","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2006 international symposium on Low power electronics and design - ISLPED '06","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2081795747","https://openalex.org/W1757458251","https://openalex.org/W2093304652","https://openalex.org/W2536345109","https://openalex.org/W2098316714","https://openalex.org/W2129785295","https://openalex.org/W4389672975","https://openalex.org/W1963851171","https://openalex.org/W1987513258","https://openalex.org/W2105463171"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"identify":[4],"the":[5,22],"key":[6],"challenges":[7],"that":[8,17],"oppose":[9],"sub-threshold":[10],"circuit":[11],"design":[12],"and":[13],"describe":[14],"fabricated":[15],"chips":[16],"verify":[18],"techniques":[19],"for":[20],"overcoming":[21],"challenges.":[23]},"counts_by_year":[{"year":2026,"cited_by_count":3},{"year":2025,"cited_by_count":6},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":6},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":7},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":6},{"year":2014,"cited_by_count":8},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":5}],"updated_date":"2026-07-19T07:52:34.831488","created_date":"2025-10-10T00:00:00"}
