{"id":"https://openalex.org/W2094776163","doi":"https://doi.org/10.1145/1165573.1165630","title":"Input-specific dynamic power optimization for VLSI circuits","display_name":"Input-specific dynamic power optimization for VLSI circuits","publication_year":2006,"publication_date":"2006-01-01","ids":{"openalex":"https://openalex.org/W2094776163","doi":"https://doi.org/10.1145/1165573.1165630","mag":"2094776163"},"language":"en","primary_location":{"id":"doi:10.1145/1165573.1165630","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1165573.1165630","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2006 international symposium on Low power electronics and design - ISLPED '06","raw_type":"proceedings-article"},"type":"conference-abstract","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050085003","display_name":"Fei Hu","orcid":"https://orcid.org/0000-0003-4346-9477"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Fei Hu","raw_affiliation_strings":["Intel Corporation, Folsom, CA","Intel Corporation, Folsom, CA 95630, USA. frank.hu@intel.com"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Folsom, CA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Folsom, CA 95630, USA. frank.hu@intel.com","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084081268","display_name":"Vishwani D. Agrawal","orcid":"https://orcid.org/0000-0002-7121-5979"},"institutions":[{"id":"https://openalex.org/I82497590","display_name":"Auburn University","ror":"https://ror.org/02v80fc35","country_code":"US","type":"education","lineage":["https://openalex.org/I82497590"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vishwani D. Agrawal","raw_affiliation_strings":["Auburn University, Auburn, AL","Auburn University, Auburn, AL 36849, USA. vagrawal@eng.auburn.edu"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Auburn University, Auburn, AL","institution_ids":["https://openalex.org/I82497590"]},{"raw_affiliation_string":"Auburn University, Auburn, AL 36849, USA. vagrawal@eng.auburn.edu","institution_ids":["https://openalex.org/I82497590"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"232","last_page":"232"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/glitch","display_name":"Glitch","score":0.971156120300293},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6749897003173828},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6717673540115356},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5115528702735901},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.5016293525695801},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.49947428703308105},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4918479919433594},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.47141358256340027},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4692186117172241},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.46594560146331787},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.4510658085346222},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4346935451030731},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.39691320061683655},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.18681618571281433},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12914210557937622}],"concepts":[{"id":"https://openalex.org/C191287063","wikidata":"https://www.wikidata.org/wiki/Q543281","display_name":"Glitch","level":3,"score":0.971156120300293},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6749897003173828},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6717673540115356},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5115528702735901},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.5016293525695801},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.49947428703308105},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4918479919433594},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.47141358256340027},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4692186117172241},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.46594560146331787},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.4510658085346222},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4346935451030731},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.39691320061683655},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.18681618571281433},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12914210557937622},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/1165573.1165630","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1165573.1165630","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2006 international symposium on Low power electronics and design - ISLPED '06","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.117.3180","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.117.3180","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.eng.auburn.edu/~vagrawal/TALKS/hu_islped06.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.146.4604","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.146.4604","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.eng.auburn.edu/~vagrawal/TALKS/sp0158-hu.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6800000071525574}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W156881855","https://openalex.org/W1557154615","https://openalex.org/W1558050744","https://openalex.org/W1595368737","https://openalex.org/W1988904108","https://openalex.org/W2061480240","https://openalex.org/W2070958209","https://openalex.org/W2112799701","https://openalex.org/W2118946420","https://openalex.org/W2143093341","https://openalex.org/W2150435684","https://openalex.org/W2161828911","https://openalex.org/W2162211138"],"related_works":["https://openalex.org/W2102708050","https://openalex.org/W2137976184","https://openalex.org/W4301877893","https://openalex.org/W3217430545","https://openalex.org/W2083793411","https://openalex.org/W2035744377","https://openalex.org/W2088006178","https://openalex.org/W2069145203","https://openalex.org/W4312306317","https://openalex.org/W63550369"],"abstract_inverted_index":{"Literature":[0],"proposes":[1],"linear":[2],"programming":[3],"(LP)":[4],"methods":[5,16],"for":[6,21],"glitch-less":[7],"design":[8,43,100],"of":[9,19,25,50,57,81,90,116],"digital":[10],"circuits.":[11],"Considering":[12],"the":[13,54,78,114,129],"worst-case":[14],"these":[15],"ensure":[17],"absence":[18],"glitches":[20],"any":[22,91],"arbitrary":[23],"state":[24],"primary":[26],"input":[27,82],"as":[28,30],"well":[29],"internal":[31],"signals.":[32],"In":[33],"this":[34],"paper,":[35],"we":[36,69],"examine":[37],"an":[38,102],"unexplored":[39],"aspect,":[40],"i.e.,":[41],"glitch-free":[42],"with":[44,110],"respect":[45],"to":[46,122],"a":[47],"specific":[48],"set":[49,80],"vectors":[51,83],"(patterns).":[52],"Introducing":[53],"logic-level":[55],"concepts":[56],"glitch-generation":[58,61],"patterns":[59],"and":[60,108,124,132],"probability,":[62],"which":[63,77],"are":[64],"analyzable":[65],"through":[66],"logic":[67],"simulation,":[68],"remove":[70],"glitch":[71],"filtering":[72],"requirements":[73],"from":[74,101],"gates":[75],"on":[76],"given":[79],"cannot":[84],"produce":[85],"glitches.":[86],"We":[87],"relax":[88],"constraints":[89],"existing":[92],"LP":[93,103],"either":[94],"selectively":[95],"or":[96],"probabilistically.":[97],"Such":[98],"input-specific":[99],"model":[104],"without":[105],"process":[106,111],"variation":[107,112],"another":[109],"reduced":[113],"number":[115],"delay":[117],"buffer":[118],"overhead":[119],"by":[120],"up":[121],"80%":[123],"63%,":[125],"respectively,":[126],"while":[127],"maintaining":[128],"power":[130],"reduction":[131],"overall":[133],"delay.":[134]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-19T07:52:34.831488","created_date":"2025-10-10T00:00:00"}
