{"id":"https://openalex.org/W2077697662","doi":"https://doi.org/10.1145/1152154.1152197","title":"Prematerialization","display_name":"Prematerialization","publication_year":2006,"publication_date":"2006-09-16","ids":{"openalex":"https://openalex.org/W2077697662","doi":"https://doi.org/10.1145/1152154.1152197","mag":"2077697662"},"language":"en","primary_location":{"id":"doi:10.1145/1152154.1152197","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1152154.1152197","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 15th international conference on Parallel architectures and compilation techniques","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040469157","display_name":"Ivan D. Baev","orcid":null},"institutions":[{"id":"https://openalex.org/I1324840837","display_name":"Hewlett-Packard (United States)","ror":"https://ror.org/059rn9488","country_code":"US","type":"company","lineage":["https://openalex.org/I1324840837"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Ivan D. Baev","raw_affiliation_strings":["Hewlett-Packard Company, Cupertino, CA","Java, Compilers, and Tools Laboratory, Hewlett-Packard Company, 11000 Wolfe Road, Cupertino, CA 95014"],"affiliations":[{"raw_affiliation_string":"Hewlett-Packard Company, Cupertino, CA","institution_ids":["https://openalex.org/I1324840837"]},{"raw_affiliation_string":"Java, Compilers, and Tools Laboratory, Hewlett-Packard Company, 11000 Wolfe Road, Cupertino, CA 95014","institution_ids":["https://openalex.org/I1324840837"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057716594","display_name":"Richard E. Hank","orcid":null},"institutions":[{"id":"https://openalex.org/I1324840837","display_name":"Hewlett-Packard (United States)","ror":"https://ror.org/059rn9488","country_code":"US","type":"company","lineage":["https://openalex.org/I1324840837"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Richard E. Hank","raw_affiliation_strings":["Hewlett-Packard Company, Cupertino, CA","Java, Compilers, and Tools Laboratory, Hewlett-Packard Company, 11000 Wolfe Road, Cupertino, CA 95014"],"affiliations":[{"raw_affiliation_string":"Hewlett-Packard Company, Cupertino, CA","institution_ids":["https://openalex.org/I1324840837"]},{"raw_affiliation_string":"Java, Compilers, and Tools Laboratory, Hewlett-Packard Company, 11000 Wolfe Road, Cupertino, CA 95014","institution_ids":["https://openalex.org/I1324840837"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5047006331","display_name":"David H. Gross","orcid":null},"institutions":[{"id":"https://openalex.org/I1324840837","display_name":"Hewlett-Packard (United States)","ror":"https://ror.org/059rn9488","country_code":"US","type":"company","lineage":["https://openalex.org/I1324840837"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David H. Gross","raw_affiliation_strings":["Hewlett-Packard Company, Cupertino, CA","Java, Compilers, and Tools Laboratory, Hewlett-Packard Company, 11000 Wolfe Road, Cupertino, CA 95014"],"affiliations":[{"raw_affiliation_string":"Hewlett-Packard Company, Cupertino, CA","institution_ids":["https://openalex.org/I1324840837"]},{"raw_affiliation_string":"Java, Compilers, and Tools Laboratory, Hewlett-Packard Company, 11000 Wolfe Road, Cupertino, CA 95014","institution_ids":["https://openalex.org/I1324840837"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5040469157"],"corresponding_institution_ids":["https://openalex.org/I1324840837"],"apc_list":null,"apc_paid":null,"fwci":0.5575,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.65332062,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"285","last_page":"294"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.9259195327758789},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8408266305923462},{"id":"https://openalex.org/keywords/very-long-instruction-word","display_name":"Very long instruction word","score":0.6060529351234436},{"id":"https://openalex.org/keywords/allocator","display_name":"Allocator","score":0.6047005653381348},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.5852245092391968},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5697593688964844},{"id":"https://openalex.org/keywords/instruction-scheduling","display_name":"Instruction scheduling","score":0.541952908039093},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.5134004354476929},{"id":"https://openalex.org/keywords/processor-register","display_name":"Processor register","score":0.4950248599052429},{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.4696680009365082},{"id":"https://openalex.org/keywords/optimizing-compiler","display_name":"Optimizing compiler","score":0.45639556646347046},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.4527469277381897},{"id":"https://openalex.org/keywords/nop","display_name":"NOP","score":0.4206054210662842},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3487818241119385},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.3359241485595703},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.28731533885002136},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.15908899903297424},{"id":"https://openalex.org/keywords/dynamic-priority-scheduling","display_name":"Dynamic priority scheduling","score":0.13823142647743225},{"id":"https://openalex.org/keywords/memory-address","display_name":"Memory address","score":0.07991302013397217}],"concepts":[{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.9259195327758789},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8408266305923462},{"id":"https://openalex.org/C170595534","wikidata":"https://www.wikidata.org/wiki/Q249743","display_name":"Very long instruction word","level":2,"score":0.6060529351234436},{"id":"https://openalex.org/C162262903","wikidata":"https://www.wikidata.org/wiki/Q343527","display_name":"Allocator","level":2,"score":0.6047005653381348},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.5852245092391968},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5697593688964844},{"id":"https://openalex.org/C73564150","wikidata":"https://www.wikidata.org/wiki/Q11417093","display_name":"Instruction scheduling","level":5,"score":0.541952908039093},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.5134004354476929},{"id":"https://openalex.org/C2871975","wikidata":"https://www.wikidata.org/wiki/Q187466","display_name":"Processor register","level":4,"score":0.4950248599052429},{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.4696680009365082},{"id":"https://openalex.org/C190902152","wikidata":"https://www.wikidata.org/wiki/Q1325106","display_name":"Optimizing compiler","level":3,"score":0.45639556646347046},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.4527469277381897},{"id":"https://openalex.org/C159023312","wikidata":"https://www.wikidata.org/wiki/Q409513","display_name":"NOP","level":3,"score":0.4206054210662842},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3487818241119385},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.3359241485595703},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.28731533885002136},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.15908899903297424},{"id":"https://openalex.org/C107568181","wikidata":"https://www.wikidata.org/wiki/Q5319000","display_name":"Dynamic priority scheduling","level":3,"score":0.13823142647743225},{"id":"https://openalex.org/C153247305","wikidata":"https://www.wikidata.org/wiki/Q835713","display_name":"Memory address","level":3,"score":0.07991302013397217},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C170493617","wikidata":"https://www.wikidata.org/wiki/Q208467","display_name":"Receptor","level":2,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C119948110","wikidata":"https://www.wikidata.org/wiki/Q7858726","display_name":"Two-level scheduling","level":4,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1152154.1152197","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1152154.1152197","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 15th international conference on Parallel architectures and compilation techniques","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W51701494","https://openalex.org/W163803696","https://openalex.org/W1498962072","https://openalex.org/W1523901979","https://openalex.org/W1552370403","https://openalex.org/W1585371887","https://openalex.org/W1881127524","https://openalex.org/W1977290744","https://openalex.org/W2044636417","https://openalex.org/W2084451631","https://openalex.org/W2120812270","https://openalex.org/W2122230401","https://openalex.org/W2914237411","https://openalex.org/W3136151461","https://openalex.org/W3148529197","https://openalex.org/W4234787094","https://openalex.org/W6639532040"],"related_works":["https://openalex.org/W4252189340","https://openalex.org/W2104533913","https://openalex.org/W4231369653","https://openalex.org/W2168354894","https://openalex.org/W4253173659","https://openalex.org/W182448324","https://openalex.org/W2059399861","https://openalex.org/W4237472977","https://openalex.org/W4236145149","https://openalex.org/W2127650532"],"abstract_inverted_index":{"Modern":[0],"compiler":[1],"transformations":[2],"that":[3,156,182],"eliminate":[4,63],"redundant":[5],"computations":[6],"or":[7,61,113],"reorder":[8],"instructions,":[9],"such":[10,73],"as":[11,74],"partial":[12],"redundancy":[13],"elimination":[14],"and":[15,30,78,98,106,142,161],"instruction":[16],"scheduling,":[17],"are":[18,157],"very":[19],"effective":[20,187],"in":[21,170,188,193],"improving":[22],"application":[23],"performance":[24],"but":[25],"tend":[26],"to":[27,48,117,125,145,159,164],"create":[28],"longer":[29],"potentially":[31],"more":[32,114],"complex":[33],"live":[34,75,104,126,154],"ranges.":[35],"Typically":[36],"the":[37,42,49,64,118,137,175,183],"task":[38],"of":[39,55,66,139],"dealing":[40],"with":[41,94],"increased":[43],"register":[44,50,89,132,146,150,190],"pressure":[45,90,191],"is":[46,123,186],"left":[47],"allocator.":[51],"To":[52],"avoid":[53],"introduction":[54],"spill":[56],"code":[57],"which":[58],"can":[59],"reduce":[60],"completely":[62],"benefit":[65],"earlier":[67],"optimizations,":[68],"researchers":[69],"have":[70,167],"developed":[71],"techniques":[72],"range":[76],"splitting":[77],"rematerializatio.This":[79],"paper":[80],"describes":[81],"prematerialization":[82,169],"(PM),":[83],"a":[84],"novel":[85],"method":[86],"for":[87,91,129,174],"reducing":[88,189],"VLIW":[92],"architectures":[93],"nop":[95,140],"instructions.":[96],"PM":[97,134,148],"rematerialization":[99,122],"both":[100],"select":[101],"\"never":[102],"killed\"":[103],"ranges":[105,127,155],"break":[107],"them":[108],"up":[109],"by":[110,152],"introducing":[111],"one":[112],"definitions":[115],"close":[116],"uses.":[119],"However,":[120],"while":[121],"applied":[124],"selected":[128],"spilling":[130],"during":[131],"allocation,":[133],"relies":[135],"on":[136],"availability":[138],"instructions":[141],"occurs":[143],"prior":[144],"allocation.":[147],"simplifies":[149],"allocation":[151],"creating":[153],"easier":[158],"color":[160],"less":[162],"likely":[163],"spill.":[165],"We":[166],"implemented":[168],"HP-UX":[171],"production":[172],"compilers":[173],"Intel\u00ae":[176],"Itanium\u00ae":[177],"architecture.":[178],"Performance":[179],"evaluation":[180],"indicates":[181],"proposed":[184],"technique":[185],"inherent":[192],"highly":[194],"optimized":[195],"code.":[196]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2016-06-24T00:00:00"}
