{"id":"https://openalex.org/W2155632738","doi":"https://doi.org/10.1145/1150343.1150396","title":"Using a software testing technique to identify registers for partial scan implementation","display_name":"Using a software testing technique to identify registers for partial scan implementation","publication_year":2006,"publication_date":"2006-08-28","ids":{"openalex":"https://openalex.org/W2155632738","doi":"https://doi.org/10.1145/1150343.1150396","mag":"2155632738"},"language":"en","primary_location":{"id":"doi:10.1145/1150343.1150396","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1150343.1150396","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 19th annual symposium on Integrated circuits and systems design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5018136636","display_name":"Margrit Reni Krug","orcid":null},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Margrit R. Krug","raw_affiliation_strings":["UFRGS, Porto Alegre - Brazil"],"affiliations":[{"raw_affiliation_string":"UFRGS, Porto Alegre - Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052263331","display_name":"Marcelo S. Moraes","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Marcelo S. Moraes","raw_affiliation_strings":["CEITEC, Porto Alegre - Brazil"],"affiliations":[{"raw_affiliation_string":"CEITEC, Porto Alegre - Brazil","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5105973341","display_name":"Marcelo Lubaszewski","orcid":null},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Marcelo S. Lubaszewski","raw_affiliation_strings":["UFRGS, Porto Alegre - Brazil"],"affiliations":[{"raw_affiliation_string":"UFRGS, Porto Alegre - Brazil","institution_ids":["https://openalex.org/I130442723"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5018136636"],"corresponding_institution_ids":["https://openalex.org/I130442723"],"apc_list":null,"apc_paid":null,"fwci":0.5575,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.68064824,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"208","last_page":"213"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.8923435211181641},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.7628751397132874},{"id":"https://openalex.org/keywords/observability","display_name":"Observability","score":0.761679470539093},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7206945419311523},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.6661468744277954},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.630635142326355},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.5753582715988159},{"id":"https://openalex.org/keywords/code-coverage","display_name":"Code coverage","score":0.5112438201904297},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.5102286338806152},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4911811053752899},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.45196446776390076},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.420726478099823},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3911835551261902},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3851189911365509},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.34464848041534424},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3286072909832001},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3071334958076477},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.23254764080047607},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.21947601437568665},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1607210338115692}],"concepts":[{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.8923435211181641},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.7628751397132874},{"id":"https://openalex.org/C36299963","wikidata":"https://www.wikidata.org/wiki/Q1369844","display_name":"Observability","level":2,"score":0.761679470539093},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7206945419311523},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.6661468744277954},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.630635142326355},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.5753582715988159},{"id":"https://openalex.org/C53942775","wikidata":"https://www.wikidata.org/wiki/Q1211721","display_name":"Code coverage","level":3,"score":0.5112438201904297},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5102286338806152},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4911811053752899},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.45196446776390076},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.420726478099823},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3911835551261902},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3851189911365509},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34464848041534424},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3286072909832001},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3071334958076477},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.23254764080047607},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.21947601437568665},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1607210338115692},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C28826006","wikidata":"https://www.wikidata.org/wiki/Q33521","display_name":"Applied mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1150343.1150396","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1150343.1150396","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 19th annual symposium on Integrated circuits and systems design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4399999976158142,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W150374354","https://openalex.org/W1513787653","https://openalex.org/W1598818557","https://openalex.org/W1910876692","https://openalex.org/W1972173228","https://openalex.org/W1983621102","https://openalex.org/W2032997462","https://openalex.org/W2054933860","https://openalex.org/W2055795571","https://openalex.org/W2072555249","https://openalex.org/W2099096493","https://openalex.org/W2108625427","https://openalex.org/W2135129887","https://openalex.org/W2140826730","https://openalex.org/W2149406149","https://openalex.org/W2152406824","https://openalex.org/W2155298431","https://openalex.org/W2603178913","https://openalex.org/W2903128886","https://openalex.org/W3010856131","https://openalex.org/W4243539966"],"related_works":["https://openalex.org/W2107525390","https://openalex.org/W2157191248","https://openalex.org/W2765347974","https://openalex.org/W2553035740","https://openalex.org/W2150046587","https://openalex.org/W2142405811","https://openalex.org/W2114980936","https://openalex.org/W2189059878","https://openalex.org/W2168652618","https://openalex.org/W2127247647"],"abstract_inverted_index":{"Scan":[0],"design":[1,54],"has":[2],"been":[3],"widely":[4],"used":[5,44],"to":[6,46,63,68,80,132],"ease":[7],"test":[8],"generation":[9],"process":[10],"for":[11,117],"digital":[12],"circuits.":[13],"Although":[14],"full":[15],"scan":[16,40,72,110],"approach":[17,99],"results":[18,114],"in":[19,108,129],"high":[20,102],"fault":[21,103],"coverage":[22,104],"while":[23,52],"reducing":[24],"ATPG":[25],"effort,":[26],"it":[27],"introduces":[28],"area":[29],"and":[30],"performance":[31],"overheads":[32],"that":[33,91,97],"are":[34],"most":[35],"times":[36],"unacceptable.":[37],"Hence,":[38],"partial":[39,71,134],"is":[41,122],"a":[42,61,70,76,101],"commonly":[43],"technique":[45,79,121],"improve":[47],"testability":[48],"of":[49,86],"sequential":[50,65],"circuits":[51],"respecting":[53],"constraints.":[55],"In":[56],"this":[57],"paper,":[58],"we":[59],"present":[60],"method":[62],"select":[64],"elements":[66],"(flip-flops)":[67],"compose":[69,133],"chain.":[73,111],"We":[74],"use":[75],"software":[77],"engineering":[78],"identify":[81],"internal":[82],"variables":[83],"or":[84],"signals":[85],"the":[87,109],"circuit's":[88],"behavioral":[89],"description":[90],"have":[92],"low":[93],"observability.":[94],"Experiments":[95],"demonstrate":[96],"our":[98],"achieves":[100],"including":[105],"few":[106],"flip-flops":[107,131],"Moreover,":[112],"comparative":[113],"show":[115],"that,":[116],"complex":[118],"circuits,":[119],"proposed":[120],"more":[123],"efficient":[124],"than":[125],"some":[126],"classical":[127],"methods":[128],"selecting":[130],"scan.":[135]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
