{"id":"https://openalex.org/W2097845952","doi":"https://doi.org/10.1145/1146909.1147190","title":"A new LP based incremental timing driven placement for high performance designs","display_name":"A new LP based incremental timing driven placement for high performance designs","publication_year":2006,"publication_date":"2006-01-01","ids":{"openalex":"https://openalex.org/W2097845952","doi":"https://doi.org/10.1145/1146909.1147190","mag":"2097845952"},"language":"en","primary_location":{"id":"doi:10.1145/1146909.1147190","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1146909.1147190","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 43rd annual conference on Design automation  - DAC '06","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002713029","display_name":"Tao Luo","orcid":"https://orcid.org/0000-0003-4870-5942"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Tao Luo","raw_affiliation_strings":["University of Texas at Austin, Austin, TX","Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"University of Texas at Austin, Austin, TX","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065044300","display_name":"David M. Newmark","orcid":null},"institutions":[{"id":"https://openalex.org/I4210137977","display_name":"Advanced Micro Devices (United States)","ror":"https://ror.org/04kd6c783","country_code":"US","type":"company","lineage":["https://openalex.org/I4210137977"]},{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Newmark","raw_affiliation_strings":["Advanced Micro Devices, Austin, TX","Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Advanced Micro Devices, Austin, TX","institution_ids":["https://openalex.org/I4210137977"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011883763","display_name":"David Z. Pan","orcid":"https://orcid.org/0000-0002-5705-2501"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Z. Pan","raw_affiliation_strings":["University of Texas at Austin, Austin, TX","Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"University of Texas at Austin, Austin, TX","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5002713029"],"corresponding_institution_ids":["https://openalex.org/I86519309"],"apc_list":null,"apc_paid":null,"fwci":6.1294,"has_fulltext":false,"cited_by_count":41,"citation_normalized_percentile":{"value":0.96391471,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1115","last_page":"1115"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7124033570289612},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.6428731083869934},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.5602322220802307},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.48902973532676697},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4751177430152893},{"id":"https://openalex.org/keywords/criticality","display_name":"Criticality","score":0.458458811044693},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.45642775297164917},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.4471184313297272},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.43165531754493713},{"id":"https://openalex.org/keywords/linear-programming","display_name":"Linear programming","score":0.4287109971046448},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.33835312724113464},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2797923684120178},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2453187108039856},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1232677698135376},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08600914478302002}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7124033570289612},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.6428731083869934},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.5602322220802307},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.48902973532676697},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4751177430152893},{"id":"https://openalex.org/C125611927","wikidata":"https://www.wikidata.org/wiki/Q17008131","display_name":"Criticality","level":2,"score":0.458458811044693},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.45642775297164917},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.4471184313297272},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.43165531754493713},{"id":"https://openalex.org/C41045048","wikidata":"https://www.wikidata.org/wiki/Q202843","display_name":"Linear programming","level":2,"score":0.4287109971046448},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.33835312724113464},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2797923684120178},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2453187108039856},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1232677698135376},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08600914478302002},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C185544564","wikidata":"https://www.wikidata.org/wiki/Q81197","display_name":"Nuclear physics","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/1146909.1147190","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1146909.1147190","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 43rd annual conference on Design automation  - DAC '06","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.91.7545","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.91.7545","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://domino.research.ibm.com/acas/w3www_acas.nsf/images/conf06/$FILE/dpan.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.97.5912","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.97.5912","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cerc.utexas.edu/utda/publications/dac06_place.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1970214014","https://openalex.org/W1984588379","https://openalex.org/W1996678568","https://openalex.org/W2003764518","https://openalex.org/W2018503585","https://openalex.org/W2030852227","https://openalex.org/W2048796234","https://openalex.org/W2099108222","https://openalex.org/W2102182481","https://openalex.org/W2103223568","https://openalex.org/W2107966189","https://openalex.org/W2108411416","https://openalex.org/W2109753853","https://openalex.org/W2111046960","https://openalex.org/W2121244114","https://openalex.org/W2149663872","https://openalex.org/W2152340280","https://openalex.org/W2156340730","https://openalex.org/W2156568500","https://openalex.org/W2163763728","https://openalex.org/W2169695288","https://openalex.org/W2179314520","https://openalex.org/W2249143245"],"related_works":["https://openalex.org/W2123973634","https://openalex.org/W4235978579","https://openalex.org/W202875565","https://openalex.org/W2004000834","https://openalex.org/W4229446324","https://openalex.org/W4214664648","https://openalex.org/W2083934283","https://openalex.org/W2092607907","https://openalex.org/W4235807419","https://openalex.org/W2158805860"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"propose":[4],"a":[5,79,85,105,112],"new":[6],"linear":[7],"programming":[8],"based":[9],"timing":[10,47,86,92,121],"driven":[11,48],"placement":[12],"framework":[13,20],"for":[14,95],"high":[15,96],"performance":[16,97],"designs.":[17,98],"Our":[18,50,99],"LP":[19,51],"is":[21],"mainly":[22],"net-based,":[23],"but":[24,61],"it":[25,38],"takes":[26],"advantage":[27],"of":[28,43,107],"the":[29,58,69,73],"path-based":[30,46],"delay":[31],"sensitivity":[32],"with":[33],"limited-stage":[34],"slew":[35],"propagation,":[36],"thus":[37],"enjoys":[39],"certain":[40],"hybrid":[41],"feature":[42],"net":[44],"and":[45,115],"placement.":[49],"formulation":[52],"considers":[53],"not":[54],"only":[55],"cells":[56,63],"on":[57,104,122],"critical":[59,70],"paths,":[60],"also":[62],"that":[64],"are":[65],"logically":[66],"adjacent":[67],"to":[68,90,117],"paths":[71],"(i.e.,":[72],"criticality":[74],"ad":[75],"jacency":[76],"network)":[77],"in":[78,93],"unified":[80],"manner.":[81],"We":[82],"further":[83],"present":[84],"aware":[87],"spreading":[88],"method":[89],"preserve":[91],"legalization":[94],"algorithm":[100],"has":[101],"been":[102],"tested":[103],"set":[106],"65nm":[108],"industry":[109],"circuits":[110],"from":[111],"multi-GHz":[113],"microprocessor,":[114],"shown":[116],"achieve":[118],"much":[119],"improved":[120],"hand-tuned":[123],"circuits.":[124]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":7},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":5}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
