{"id":"https://openalex.org/W2145179653","doi":"https://doi.org/10.1145/1146909.1147093","title":"Topology aware mapping of logic functions onto nanowire-based crossbar architectures","display_name":"Topology aware mapping of logic functions onto nanowire-based crossbar architectures","publication_year":2006,"publication_date":"2006-01-01","ids":{"openalex":"https://openalex.org/W2145179653","doi":"https://doi.org/10.1145/1146909.1147093","mag":"2145179653"},"language":"en","primary_location":{"id":"doi:10.1145/1146909.1147093","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1146909.1147093","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 43rd annual conference on Design automation  - DAC '06","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030760900","display_name":"Wenjing Rao","orcid":"https://orcid.org/0000-0001-8633-9512"},"institutions":[{"id":"https://openalex.org/I2800935791","display_name":"UC San Diego Health System","ror":"https://ror.org/01kbfgm16","country_code":"US","type":"healthcare","lineage":["https://openalex.org/I2800935791"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Wenjing Rao","raw_affiliation_strings":["UC San Diego","UC San Diego;"],"affiliations":[{"raw_affiliation_string":"UC San Diego","institution_ids":["https://openalex.org/I2800935791"]},{"raw_affiliation_string":"UC San Diego;","institution_ids":["https://openalex.org/I2800935791"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006811625","display_name":"Alex Orailo\u011flu","orcid":"https://orcid.org/0000-0002-6104-3923"},"institutions":[{"id":"https://openalex.org/I2800935791","display_name":"UC San Diego Health System","ror":"https://ror.org/01kbfgm16","country_code":"US","type":"healthcare","lineage":["https://openalex.org/I2800935791"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Alex Orailoglu","raw_affiliation_strings":["UC San Diego","UC San Diego;"],"affiliations":[{"raw_affiliation_string":"UC San Diego","institution_ids":["https://openalex.org/I2800935791"]},{"raw_affiliation_string":"UC San Diego;","institution_ids":["https://openalex.org/I2800935791"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059648257","display_name":"Ramesh Karri","orcid":"https://orcid.org/0000-0001-7989-5617"},"institutions":[{"id":"https://openalex.org/I4210120584","display_name":"Polytechnic University","ror":"https://ror.org/02f0psx94","country_code":"JP","type":"education","lineage":["https://openalex.org/I4210120584"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Ramesh Karri","raw_affiliation_strings":["Polytechnic University","Electrical and Computer Engineering"],"affiliations":[{"raw_affiliation_string":"Polytechnic University","institution_ids":["https://openalex.org/I4210120584"]},{"raw_affiliation_string":"Electrical and Computer Engineering","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5030760900"],"corresponding_institution_ids":["https://openalex.org/I2800935791"],"apc_list":null,"apc_paid":null,"fwci":5.3612,"has_fulltext":false,"cited_by_count":32,"citation_normalized_percentile":{"value":0.95707763,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"723","last_page":"723"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10913","display_name":"Molecular Junctions and Nanostructures","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10913","display_name":"Molecular Junctions and Nanostructures","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11272","display_name":"Nanowire Synthesis and Applications","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.7322521805763245},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6436194181442261},{"id":"https://openalex.org/keywords/heuristics","display_name":"Heuristics","score":0.5979518294334412},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5952763557434082},{"id":"https://openalex.org/keywords/nanowire","display_name":"Nanowire","score":0.5774611234664917},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5273255705833435},{"id":"https://openalex.org/keywords/nanodevice","display_name":"Nanodevice","score":0.5018353462219238},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4814433455467224},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.4738355576992035},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.44844114780426025},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.430980920791626},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.4176729619503021},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4040508568286896},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.40301355719566345},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.353426456451416},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.31479495763778687},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.25427454710006714},{"id":"https://openalex.org/keywords/nanotechnology","display_name":"Nanotechnology","score":0.22244566679000854},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.18716487288475037},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17533361911773682},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.1658763289451599},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13700366020202637},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.09356996417045593}],"concepts":[{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.7322521805763245},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6436194181442261},{"id":"https://openalex.org/C127705205","wikidata":"https://www.wikidata.org/wiki/Q5748245","display_name":"Heuristics","level":2,"score":0.5979518294334412},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5952763557434082},{"id":"https://openalex.org/C74214498","wikidata":"https://www.wikidata.org/wiki/Q631739","display_name":"Nanowire","level":2,"score":0.5774611234664917},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5273255705833435},{"id":"https://openalex.org/C2909374376","wikidata":"https://www.wikidata.org/wiki/Q2726733","display_name":"Nanodevice","level":2,"score":0.5018353462219238},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4814433455467224},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.4738355576992035},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.44844114780426025},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.430980920791626},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.4176729619503021},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4040508568286896},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.40301355719566345},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.353426456451416},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.31479495763778687},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.25427454710006714},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.22244566679000854},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.18716487288475037},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17533361911773682},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.1658763289451599},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13700366020202637},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.09356996417045593},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/1146909.1147093","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1146909.1147093","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 43rd annual conference on Design automation  - DAC '06","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.135.2439","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.135.2439","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://ieeexplore.ieee.org/iel5/11109/35624/01688891.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.990.1926","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.990.1926","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ruf.rice.edu/%7Emobile/elec527/readings/patrick3_p723-rao.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.46000000834465027}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W2003872791","https://openalex.org/W2040057539","https://openalex.org/W2049650033","https://openalex.org/W2050111978","https://openalex.org/W2063782027","https://openalex.org/W2128181612","https://openalex.org/W2137249916","https://openalex.org/W2139399616","https://openalex.org/W2162983760","https://openalex.org/W2166095336","https://openalex.org/W2167086449","https://openalex.org/W2167807101"],"related_works":["https://openalex.org/W2789662562","https://openalex.org/W2017528947","https://openalex.org/W1553855433","https://openalex.org/W1593362825","https://openalex.org/W1529529399","https://openalex.org/W2082591327","https://openalex.org/W2155174752","https://openalex.org/W2102499515","https://openalex.org/W2171918386","https://openalex.org/W2021357106"],"abstract_inverted_index":{"Highly":[0],"regular,":[1],"nanodevice":[2],"based":[3,12],"architectures":[4,13],"have":[5],"been":[6],"proposed":[7],"to":[8,25,53,104,110],"replace":[9],"pure":[10],"CMOS":[11,18,43],"in":[14,68],"the":[15,55,59,112],"emerging":[16,33],"post":[17],"era.":[19],"Since":[20],"bottom-up":[21],"self-assembly":[22],"is":[23],"used":[24],"build":[26],"these":[27,39,69],"architectures,":[28],"regular":[29,40],"nanowire":[30,89],"crossbars":[31,70,90],"are":[32],"as":[34],"a":[35,96],"promising":[36],"candidate.":[37],"While":[38],"structures":[41],"resemble":[42],"programmable":[44],"logic":[45,49,92],"arrays":[46],"(PLAs),":[47],"PLA":[48],"synthesis":[50],"methodologies":[51],"fail":[52],"solve":[54,105],"associated":[56],"problems":[57],"since":[58],"length":[60],"and":[61,107],"connectivity":[62],"constraints":[63,80],"imposed":[64],"by":[65],"individual":[66],"nanowires":[67],"translate":[71],"into":[72],"challenges":[73],"hitherto":[74],"not":[75],"considered.":[76],"These":[77],"strict":[78],"topological":[79],"should":[81],"be":[82],"considered":[83],"while":[84],"mapping":[85],"Boolean":[86],"functions":[87],"onto":[88],"during":[91],"synthesis.":[93],"We":[94],"develop":[95],"mathematical":[97],"model":[98],"for":[99],"this":[100],"problem,":[101],"an":[102],"algorithm":[103,113],"it":[106],"three":[108],"heuristics":[109],"improve":[111],"runtime.":[114]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
