{"id":"https://openalex.org/W2150660745","doi":"https://doi.org/10.1145/1146909.1147026","title":"Register binding for clock period minimization","display_name":"Register binding for clock period minimization","publication_year":2006,"publication_date":"2006-01-01","ids":{"openalex":"https://openalex.org/W2150660745","doi":"https://doi.org/10.1145/1146909.1147026","mag":"2150660745"},"language":"en","primary_location":{"id":"doi:10.1145/1146909.1147026","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1146909.1147026","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 43rd annual conference on Design automation - DAC '06","raw_type":"proceedings-article"},"type":"conference-abstract","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060945705","display_name":"Shih-Hsu Huang","orcid":"https://orcid.org/0000-0001-8908-8384"},"institutions":[{"id":"https://openalex.org/I151221077","display_name":"Chung Yuan Christian University","ror":"https://ror.org/02w8ws377","country_code":"TW","type":"education","lineage":["https://openalex.org/I151221077"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Shih-Hsu Huang","raw_affiliation_strings":["Chung Yuan Christian University, Chung Li, Taiwan, R.O.C"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Chung Yuan Christian University, Chung Li, Taiwan, R.O.C","institution_ids":["https://openalex.org/I151221077"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059158206","display_name":"Chun-Hua Cheng","orcid":null},"institutions":[{"id":"https://openalex.org/I151221077","display_name":"Chung Yuan Christian University","ror":"https://ror.org/02w8ws377","country_code":"TW","type":"education","lineage":["https://openalex.org/I151221077"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chun-Hua Cheng","raw_affiliation_strings":["Chung Yuan Christian University, Chung Li, Taiwan, R.O.C"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Chung Yuan Christian University, Chung Li, Taiwan, R.O.C","institution_ids":["https://openalex.org/I151221077"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113627821","display_name":"Yow-Tyng Nieh","orcid":null},"institutions":[{"id":"https://openalex.org/I151221077","display_name":"Chung Yuan Christian University","ror":"https://ror.org/02w8ws377","country_code":"TW","type":"education","lineage":["https://openalex.org/I151221077"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yow-Tyng Nieh","raw_affiliation_strings":["Chung Yuan Christian University, Chung Li, Taiwan, R.O.C"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Chung Yuan Christian University, Chung Li, Taiwan, R.O.C","institution_ids":["https://openalex.org/I151221077"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5042678612","display_name":"Wei-Chieh Yu","orcid":null},"institutions":[{"id":"https://openalex.org/I151221077","display_name":"Chung Yuan Christian University","ror":"https://ror.org/02w8ws377","country_code":"TW","type":"education","lineage":["https://openalex.org/I151221077"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Wei-Chieh Yu","raw_affiliation_strings":["Chung Yuan Christian University, Chung Li, Taiwan, R.O.C"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Chung Yuan Christian University, Chung Li, Taiwan, R.O.C","institution_ids":["https://openalex.org/I151221077"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I151221077"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":24,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"439","last_page":"439"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.9188069105148315},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.7877724170684814},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.7653829455375671},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.6738734245300293},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6346554160118103},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5890449285507202},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.5832089185714722},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.5465242862701416},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.5096418857574463},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5041981935501099},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.49851059913635254},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.47206881642341614},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.43567314743995667},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.4214399755001068},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.37464994192123413},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.3711257576942444},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.32783177495002747},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3147546350955963},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13290321826934814},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08869379758834839},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07181039452552795}],"concepts":[{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.9188069105148315},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.7877724170684814},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.7653829455375671},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.6738734245300293},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6346554160118103},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5890449285507202},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.5832089185714722},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.5465242862701416},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.5096418857574463},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5041981935501099},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.49851059913635254},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.47206881642341614},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.43567314743995667},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.4214399755001068},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.37464994192123413},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3711257576942444},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.32783177495002747},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3147546350955963},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13290321826934814},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08869379758834839},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07181039452552795},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1146909.1147026","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1146909.1147026","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 43rd annual conference on Design automation - DAC '06","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.93.7418","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.93.7418","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://manga.rt.cs.tu-berlin.de/pdf/P0439.PDF","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320320879","display_name":"Deutsche Forschungsgemeinschaft","ror":"https://ror.org/018mejw64"},{"id":"https://openalex.org/F4320321040","display_name":"National Science Council","ror":"https://ror.org/02kv4zf79"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1511469799","https://openalex.org/W2011778848","https://openalex.org/W2063747323","https://openalex.org/W2093332051","https://openalex.org/W2100525812","https://openalex.org/W2114266730","https://openalex.org/W2117285153","https://openalex.org/W2129579146","https://openalex.org/W2168937479"],"related_works":["https://openalex.org/W3006003651","https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2133326759","https://openalex.org/W2040807843","https://openalex.org/W4249038728","https://openalex.org/W1564063853","https://openalex.org/W2559451387","https://openalex.org/W4230501858","https://openalex.org/W60672686"],"abstract_inverted_index":{"In":[0],"modern":[1],"high-speed":[2],"circuit":[3,19,27],"design,":[4],"the":[5,18,26,32,40,44,56,68,94,107,129,133,144],"clock":[6,35,49,85,100,134],"skew":[7,50],"has":[8,63],"been":[9],"widely":[10],"utilized":[11],"as":[12],"a":[13,64,74,104,116],"manageable":[14],"resource":[15],"to":[16,43,81,114],"improve":[17],"performance.":[20],"However,":[21],"in":[22,59,125],"high-level":[23,45,60],"synthesis":[24,46,61],"stage,":[25],"is":[28,39,113],"never":[29],"optimized":[30],"for":[31,99],"utilization":[33],"of":[34,47,96,109,132,146],"skew.":[36],"This":[37],"paper":[38],"first":[41],"attempt":[42],"non-zero":[48],"circuits.":[51],"First,":[52],"we":[53,92],"show":[54,123],"that":[55,90],"register":[57,77,97,118],"binding":[58,78,98,119],"stage":[62],"significant":[65],"impact":[66],"on":[67,89,106,143],"clocking":[69],"constraints":[70],"between":[71],"registers.":[72,147],"As":[73],"result,":[75],"different":[76,82],"solutions":[79],"lead":[80],"smallest":[83],"feasible":[84],"periods.":[86],"Then,":[87],"based":[88],"observation,":[91],"formulate":[93],"problem":[95],"period":[101,135],"minimization.":[102],"Given":[103],"constraint":[105],"number":[108,145],"registers,":[110],"our":[111],"objective":[112],"find":[115],"minimum-period":[117],"solution.":[120],"Experimental":[121],"data":[122],"that,":[124],"most":[126],"benchmark":[127],"circuits,":[128],"lower":[130],"bound":[131],"can":[136],"be":[137],"achieved":[138],"without":[139],"any":[140],"extra":[141],"overhead":[142]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2012,"cited_by_count":5}],"updated_date":"2026-08-26T07:47:46.906454","created_date":"2025-10-10T00:00:00"}
