{"id":"https://openalex.org/W2131583907","doi":"https://doi.org/10.1145/1146909.1146981","title":"Programming models and HW-SW interfaces abstraction for multi-processor SoC","display_name":"Programming models and HW-SW interfaces abstraction for multi-processor SoC","publication_year":2006,"publication_date":"2006-01-01","ids":{"openalex":"https://openalex.org/W2131583907","doi":"https://doi.org/10.1145/1146909.1146981","mag":"2131583907"},"language":"en","primary_location":{"id":"doi:10.1145/1146909.1146981","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1146909.1146981","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 43rd annual conference on Design automation  - DAC '06","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113780350","display_name":"Ahmed Jerraya","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Ahmed A. Jerraya","raw_affiliation_strings":["TIMA Laboratory, Grenoble CEDEX, France"],"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, Grenoble CEDEX, France","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029217173","display_name":"Aimen Bouchhima","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Aimen Bouchhima","raw_affiliation_strings":["TIMA Laboratory, Grenoble CEDEX, France"],"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, Grenoble CEDEX, France","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5085830369","display_name":"Fr\u00e9d\u00e9ric P\u00e9trot","orcid":"https://orcid.org/0000-0003-0624-7373"},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Fr\u00e9d\u00e9ric P\u00e9trot","raw_affiliation_strings":["TIMA Laboratory, Grenoble CEDEX, France"],"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, Grenoble CEDEX, France","institution_ids":["https://openalex.org/I4210087012"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5113780350"],"corresponding_institution_ids":["https://openalex.org/I4210087012"],"apc_list":null,"apc_paid":null,"fwci":10.5138,"has_fulltext":false,"cited_by_count":71,"citation_normalized_percentile":{"value":0.9889998,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"280","last_page":"280"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8317677974700928},{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.7729063034057617},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.5745244026184082},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5628024339675903},{"id":"https://openalex.org/keywords/programming-paradigm","display_name":"Programming paradigm","score":0.5570093393325806},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5558522343635559},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.49102330207824707},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4900999963283539},{"id":"https://openalex.org/keywords/software-framework","display_name":"Software framework","score":0.4771113693714142},{"id":"https://openalex.org/keywords/embedded-software","display_name":"Embedded software","score":0.43633538484573364},{"id":"https://openalex.org/keywords/component-based-software-engineering","display_name":"Component-based software engineering","score":0.4341670274734497},{"id":"https://openalex.org/keywords/software-design","display_name":"Software design","score":0.41722697019577026},{"id":"https://openalex.org/keywords/software-development","display_name":"Software development","score":0.3853600025177002},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.364265501499176},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.3096168041229248},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.306086927652359}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8317677974700928},{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.7729063034057617},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.5745244026184082},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5628024339675903},{"id":"https://openalex.org/C34165917","wikidata":"https://www.wikidata.org/wiki/Q188267","display_name":"Programming paradigm","level":2,"score":0.5570093393325806},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5558522343635559},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.49102330207824707},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4900999963283539},{"id":"https://openalex.org/C76518257","wikidata":"https://www.wikidata.org/wiki/Q271680","display_name":"Software framework","level":5,"score":0.4771113693714142},{"id":"https://openalex.org/C154488198","wikidata":"https://www.wikidata.org/wiki/Q1335007","display_name":"Embedded software","level":3,"score":0.43633538484573364},{"id":"https://openalex.org/C174683762","wikidata":"https://www.wikidata.org/wiki/Q609588","display_name":"Component-based software engineering","level":4,"score":0.4341670274734497},{"id":"https://openalex.org/C52913732","wikidata":"https://www.wikidata.org/wiki/Q857102","display_name":"Software design","level":4,"score":0.41722697019577026},{"id":"https://openalex.org/C529173508","wikidata":"https://www.wikidata.org/wiki/Q638608","display_name":"Software development","level":3,"score":0.3853600025177002},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.364265501499176},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3096168041229248},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.306086927652359},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/1146909.1146981","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1146909.1146981","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 43rd annual conference on Design automation  - DAC '06","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.89.3890","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.89.3890","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://manga.rt.cs.tu-berlin.de/pdf/P0280.PDF","raw_type":"text"},{"id":"pmh:oai:HAL:hal-00103520v1","is_oa":false,"landing_page_url":"https://hal.science/hal-00103520","pdf_url":null,"source":{"id":"https://openalex.org/S4406922461","display_name":"SPIRE - Sciences Po Institutional REpository","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"2006, pp.280 - 285","raw_type":"Conference papers"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.49000000953674316,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320313144","display_name":"ITEA","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W30270364","https://openalex.org/W1536710422","https://openalex.org/W1850405760","https://openalex.org/W1996142033","https://openalex.org/W2097257415","https://openalex.org/W2110447044","https://openalex.org/W2111134965","https://openalex.org/W2134919249","https://openalex.org/W2140268173","https://openalex.org/W2140582842","https://openalex.org/W2155882878","https://openalex.org/W2163075631","https://openalex.org/W2164095419","https://openalex.org/W2481725867","https://openalex.org/W3000384474","https://openalex.org/W4238272352"],"related_works":["https://openalex.org/W613069195","https://openalex.org/W3146125177","https://openalex.org/W2121150553","https://openalex.org/W2154685787","https://openalex.org/W2381752790","https://openalex.org/W2360768015","https://openalex.org/W2367803414","https://openalex.org/W1764030237","https://openalex.org/W2359736225","https://openalex.org/W1553848812"],"abstract_inverted_index":{"For":[0,107],"the":[1,6,41,47,55,66,71,95,108,111],"design":[2,48],"of":[3,20,49,60,97,113],"classic":[4,45],"computers":[5],"Parallel":[7],"programming":[8,42,72,85,116],"concept":[9],"is":[10,25],"used":[11],"to":[12,28,64,87],"abstract":[13,88],"HW/SW":[14],"interfaces":[15],"during":[16],"high":[17],"level":[18,36,115],"specification":[19],"application":[21],"software.":[22,67],"The":[23],"software":[24,37,78,92],"then":[26],"adapted":[27],"an":[29],"existing":[30],"multiprocessor":[31],"platforms":[32],"using":[33],"a":[34],"low":[35],"layers":[38],"that":[39],"implement":[40],"model.":[43],"Unlike":[44],"computers,":[46],"heterogeneous":[50,98],"MPSoC":[51,99],"includes":[52],"also":[53],"building":[54],"processors":[56],"and":[57,77,91,124],"other":[58],"kind":[59],"hardware":[61,76,90],"components":[62],"required":[63],"execute":[65],"In":[68],"this":[69],"case,":[70],"model":[73],"hides":[74],"both":[75,89],"refinements.":[79],"This":[80],"paper":[81],"deals":[82],"with":[83],"parallel":[84],"models":[86,117],"Interfaces":[93],"in":[94],"case":[96],"design.":[100],"Different":[101],"abstraction":[102],"levels":[103],"will":[104,118],"be":[105],"needed.":[106],"long":[109],"term,":[110],"use":[112],"higher":[114],"open":[119],"new":[120],"vistas":[121],"for":[122],"optimization":[123],"architecture":[125],"exploration":[126],"like":[127],"CPU/RTOS":[128],"tradeoffs.":[129]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":8},{"year":2012,"cited_by_count":5}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
