{"id":"https://openalex.org/W2142202849","doi":"https://doi.org/10.1145/1146909.1146974","title":"A multi-port current source model for multiple-input switching effects in CMOS library cells","display_name":"A multi-port current source model for multiple-input switching effects in CMOS library cells","publication_year":2006,"publication_date":"2006-01-01","ids":{"openalex":"https://openalex.org/W2142202849","doi":"https://doi.org/10.1145/1146909.1146974","mag":"2142202849"},"language":"en","primary_location":{"id":"doi:10.1145/1146909.1146974","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1146909.1146974","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 43rd annual conference on Design automation  - DAC '06","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060010506","display_name":"Chirayu Amin","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chirayu Amin","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR","Strategic CAD Laboratories, Intel Corporation, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Strategic CAD Laboratories, Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110899319","display_name":"Chandramouli Kashyap","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chandramouli Kashyap","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR","Strategic CAD Laboratories, Intel Corporation, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Strategic CAD Laboratories, Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113512269","display_name":"Noel Menezes","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Noel Menezes","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR","Strategic CAD Laboratories, Intel Corporation, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Strategic CAD Laboratories, Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037460485","display_name":"Kip Killpack","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kip Killpack","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR","Strategic CAD Laboratories, Intel Corporation, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Strategic CAD Laboratories, Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5087685981","display_name":"Eli Chiprout","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Eli Chiprout","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR","Strategic CAD Laboratories, Intel Corporation, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Strategic CAD Laboratories, Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":11.5036,"has_fulltext":false,"cited_by_count":84,"citation_normalized_percentile":{"value":0.98799541,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"247","last_page":"247"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/noise-margin","display_name":"Noise margin","score":0.5898898839950562},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5671667456626892},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.528287947177887},{"id":"https://openalex.org/keywords/nonlinear-system","display_name":"Nonlinear system","score":0.47744256258010864},{"id":"https://openalex.org/keywords/waveform","display_name":"Waveform","score":0.47227203845977783},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.46984854340553284},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3799635171890259},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3120574951171875},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.19054922461509705},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.18339332938194275},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13714894652366638}],"concepts":[{"id":"https://openalex.org/C179499742","wikidata":"https://www.wikidata.org/wiki/Q1324892","display_name":"Noise margin","level":4,"score":0.5898898839950562},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5671667456626892},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.528287947177887},{"id":"https://openalex.org/C158622935","wikidata":"https://www.wikidata.org/wiki/Q660848","display_name":"Nonlinear system","level":2,"score":0.47744256258010864},{"id":"https://openalex.org/C197424946","wikidata":"https://www.wikidata.org/wiki/Q1165717","display_name":"Waveform","level":3,"score":0.47227203845977783},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.46984854340553284},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3799635171890259},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3120574951171875},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.19054922461509705},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.18339332938194275},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13714894652366638},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.0},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C554190296","wikidata":"https://www.wikidata.org/wiki/Q47528","display_name":"Radar","level":2,"score":0.0},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1146909.1146974","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1146909.1146974","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 43rd annual conference on Design automation  - DAC '06","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320330944","display_name":"Nature","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1547254974","https://openalex.org/W1562054836","https://openalex.org/W1964572906","https://openalex.org/W2104726505","https://openalex.org/W2105904555","https://openalex.org/W2108816571","https://openalex.org/W2115296652","https://openalex.org/W2117994896","https://openalex.org/W2128406327","https://openalex.org/W2133268384","https://openalex.org/W2142659896","https://openalex.org/W2150382568","https://openalex.org/W2155302120","https://openalex.org/W2163626738"],"related_works":["https://openalex.org/W3111172706","https://openalex.org/W2115030441","https://openalex.org/W2652100805","https://openalex.org/W2147578878","https://openalex.org/W2159990075","https://openalex.org/W2799149877","https://openalex.org/W2187808779","https://openalex.org/W2614149677","https://openalex.org/W1496660757","https://openalex.org/W2171331836"],"abstract_inverted_index":{"The":[0,34],"problem":[1],"of":[2,45,54,62,87,107,137,163],"multiple-input":[3],"switching":[4,109,113],"(MIS)":[5],"has":[6],"been":[7],"mostly":[8],"ignored":[9],"by":[10],"the":[11,48,94,135,150,164],"timing":[12,19],"CAD":[13],"community.":[14],"Not":[15],"modeling":[16,61,122],"MIS":[17],"for":[18,159],"can":[20,101],"result":[21],"in":[22,28,119],"as":[23,25,60],"much":[24],"100%":[26],"error":[27],"stage":[29],"delay":[30,77,126,153],"and":[31,127,154,161,196],"slew":[32],"calculation.":[33],"impact":[35,70],"is":[36,117,175],"especially":[37],"severe":[38],"on":[39,71,139],"stages":[40],"immediately":[41],"after":[42],"a":[43,51,140,199],"bank":[44],"flops,":[46],"where":[47],"inputs":[49],"have":[50],"high":[52],"probability":[53],"arriving":[55],"simultaneously.":[56],"Other":[57],"problems":[58,123],"such":[59],"interconnect":[63],"loads,":[64],"complex":[65],"(nonlinear/non-monotonic)":[66],"input":[67,75],"waveforms,":[68],"power-droop":[69],"cell":[72],"delay,":[73],"nonlinear":[74],"capacitances,":[76],"variations":[78],"due":[79],"to":[80],"cross-capacitance,":[81],"etc.":[82],"are":[83,130],"also":[84,168],"known":[85],"sources":[86],"error.":[88,189],"In":[89],"this":[90],"paper,":[91],"we":[92],"introduce":[93],"multi-port":[95],"current":[96],"source":[97],"model":[98,151,179],"(MCSM).":[99],"MCSM":[100,116,138,174,190],"efficiently":[102],"handle":[103],"an":[104,176],"arbitrary":[105],"number":[106],"simultaneously":[108],"inputs,":[110],"including":[111],"single-input":[112],"(SIS).":[114],"Moreover,":[115],"comprehensive":[118],"that":[120,171,173],"other":[121],"associated":[124],"with":[125],"noise":[128],"computation":[129],"elegantly":[131],"covered.":[132],"We":[133,167],"demonstrate":[134],"applicability":[136],"large":[141],"65":[142],"nm":[143],"industrial":[144],"test-case.":[145],"For":[146],"cells":[147],"experiencing":[148],"MIS,":[149],"yields":[152],"slew-rate":[155],"errors":[156],"within":[157],"\u00b15%":[158],"88.3%":[160],"93.0%":[162],"cases,":[165],"respectively.":[166],"present":[169],"data":[170],"show":[172],"effective":[177],"receiver":[178],"which":[180],"captures":[181],"active":[182],"loading":[183],"effects":[184],"without":[185],"incurring":[186],"significant":[187],"additional":[188],"makes":[191],"combined":[192],"cell-level":[193],"timing,":[194],"noise,":[195],"power":[197],"analysis":[198],"possibility.":[200]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":5},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":9},{"year":2012,"cited_by_count":8}],"updated_date":"2026-06-19T17:40:00.097472","created_date":"2025-10-10T00:00:00"}