{"id":"https://openalex.org/W2144495128","doi":"https://doi.org/10.1145/1146909.1146938","title":"Towards a C++-based design methodology facilitating sequential equivalence checking","display_name":"Towards a C++-based design methodology facilitating sequential equivalence checking","publication_year":2006,"publication_date":"2006-01-01","ids":{"openalex":"https://openalex.org/W2144495128","doi":"https://doi.org/10.1145/1146909.1146938","mag":"2144495128"},"language":"en","primary_location":{"id":"doi:10.1145/1146909.1146938","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1146909.1146938","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 43rd annual conference on Design automation  - DAC '06","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5077958530","display_name":"P. Georgelin","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104693","display_name":"STMicroelectronics (France)","ror":"https://ror.org/01c74sd89","country_code":"FR","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]},{"id":"https://openalex.org/I131827901","display_name":"STMicroelectronics (Switzerland)","ror":"https://ror.org/00wm3b005","country_code":"CH","type":"company","lineage":["https://openalex.org/I131827901"]}],"countries":["CH","FR"],"is_corresponding":true,"raw_author_name":"Philippe Georgelin","raw_affiliation_strings":["STMicroelectronics, Crolles, France","[STMicroelectronics Crolles France]"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Crolles, France","institution_ids":["https://openalex.org/I4210104693"]},{"raw_affiliation_string":"[STMicroelectronics Crolles France]","institution_ids":["https://openalex.org/I131827901"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113685480","display_name":"Venkat Raghavan Krishnaswamy","orcid":"https://orcid.org/0000-0002-9951-3740"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Venkat Krishnaswamy","raw_affiliation_strings":["Calypto Design Systems, Inc., Santa Clara"],"affiliations":[{"raw_affiliation_string":"Calypto Design Systems, Inc., Santa Clara","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5077958530"],"corresponding_institution_ids":["https://openalex.org/I131827901","https://openalex.org/I4210104693"],"apc_list":null,"apc_paid":null,"fwci":1.3081,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.81297036,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"93","last_page":"93"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/formal-equivalence-checking","display_name":"Formal equivalence checking","score":0.8291157484054565},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7761572003364563},{"id":"https://openalex.org/keywords/model-checking","display_name":"Model checking","score":0.6565501093864441},{"id":"https://openalex.org/keywords/usable","display_name":"USable","score":0.6429954767227173},{"id":"https://openalex.org/keywords/equivalence","display_name":"Equivalence (formal languages)","score":0.6013743281364441},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.5999029278755188},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.5501381754875183},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.5290557146072388},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.5052765011787415},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.49909019470214844},{"id":"https://openalex.org/keywords/formal-methods","display_name":"Formal methods","score":0.4750361740589142},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4303334355354309},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.35845044255256653},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2781240940093994},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.13279610872268677}],"concepts":[{"id":"https://openalex.org/C96654402","wikidata":"https://www.wikidata.org/wiki/Q5469962","display_name":"Formal equivalence checking","level":3,"score":0.8291157484054565},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7761572003364563},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.6565501093864441},{"id":"https://openalex.org/C2780615836","wikidata":"https://www.wikidata.org/wiki/Q2471869","display_name":"USable","level":2,"score":0.6429954767227173},{"id":"https://openalex.org/C2780069185","wikidata":"https://www.wikidata.org/wiki/Q7977945","display_name":"Equivalence (formal languages)","level":2,"score":0.6013743281364441},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.5999029278755188},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.5501381754875183},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.5290557146072388},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.5052765011787415},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.49909019470214844},{"id":"https://openalex.org/C75606506","wikidata":"https://www.wikidata.org/wiki/Q1049183","display_name":"Formal methods","level":2,"score":0.4750361740589142},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4303334355354309},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35845044255256653},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2781240940093994},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.13279610872268677},{"id":"https://openalex.org/C136764020","wikidata":"https://www.wikidata.org/wiki/Q466","display_name":"World Wide Web","level":1,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1146909.1146938","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1146909.1146938","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 43rd annual conference on Design automation  - DAC '06","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5699999928474426,"id":"https://metadata.un.org/sdg/4","display_name":"Quality Education"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W1536710422","https://openalex.org/W2481725867"],"related_works":["https://openalex.org/W2152752131","https://openalex.org/W2037121848","https://openalex.org/W113732979","https://openalex.org/W1547517160","https://openalex.org/W2060070465","https://openalex.org/W2391979747","https://openalex.org/W2534958226","https://openalex.org/W2088632015","https://openalex.org/W2981877881","https://openalex.org/W1483297389"],"abstract_inverted_index":{"It":[0],"has":[1],"long":[2],"been":[3],"the":[4,22,69,89,104,107],"practice":[5],"to":[6,38,50,67,102],"create":[7],"models":[8,28,74],"in":[9,21,31,75],"C":[10],"or":[11],"C++":[12,32,76],"for":[13,83],"architectural":[14],"studies,":[15],"software":[16],"prototyping":[17],"and":[18],"RTL":[19,87],"verification":[20,85],"design":[23],"of":[24,55,72,86,91,106],"Systems-on-Chip":[25],"(SoC).":[26],"These":[27],"are":[29,81],"written":[30],"primarily":[33],"because":[34,46],"it":[35,47],"is":[36,48,100],"possible":[37],"achieve":[39],"very":[40],"high":[41,53],"simulation":[42],"speeds,":[43],"but":[44],"also":[45],"productive":[49],"code":[51],"at":[52],"levels":[54],"abstraction.":[56],"In":[57],"this":[58],"paper":[59],"we":[60],"present":[61],"a":[62],"modeling":[63],"methodology":[64],"that":[65,79],"continues":[66],"exploit":[68],"inherent":[70],"advantages":[71],"writing":[73],"while":[77],"ensuring":[78],"they":[80],"usable":[82],"formal":[84],"through":[88],"use":[90],"sequential":[92],"equivalence":[93],"checking":[94],"technology.":[95],"An":[96],"industrial":[97],"case":[98],"study":[99],"presented":[101],"show":[103],"validity":[105],"approach.":[108]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
