{"id":"https://openalex.org/W2098445357","doi":"https://doi.org/10.1145/1127908.1128003","title":"Circuit architecture for low-power race-free programmable logic arrays","display_name":"Circuit architecture for low-power race-free programmable logic arrays","publication_year":2006,"publication_date":"2006-04-30","ids":{"openalex":"https://openalex.org/W2098445357","doi":"https://doi.org/10.1145/1127908.1128003","mag":"2098445357"},"language":"en","primary_location":{"id":"doi:10.1145/1127908.1128003","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1127908.1128003","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 16th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072861402","display_name":"Giby Samson","orcid":"https://orcid.org/0000-0001-5227-516X"},"institutions":[{"id":"https://openalex.org/I55732556","display_name":"Arizona State University","ror":"https://ror.org/03efmqc40","country_code":"US","type":"education","lineage":["https://openalex.org/I55732556"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Giby Samson","raw_affiliation_strings":["Arizona State University, Tempe, Arizona"],"affiliations":[{"raw_affiliation_string":"Arizona State University, Tempe, Arizona","institution_ids":["https://openalex.org/I55732556"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5015329523","display_name":"Lawrence T. Clark","orcid":"https://orcid.org/0000-0001-7741-6512"},"institutions":[{"id":"https://openalex.org/I55732556","display_name":"Arizona State University","ror":"https://ror.org/03efmqc40","country_code":"US","type":"education","lineage":["https://openalex.org/I55732556"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Lawrence T. Clark","raw_affiliation_strings":["Arizona State University, Tempe, Arizona"],"affiliations":[{"raw_affiliation_string":"Arizona State University, Tempe, Arizona","institution_ids":["https://openalex.org/I55732556"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5072861402"],"corresponding_institution_ids":["https://openalex.org/I55732556"],"apc_list":null,"apc_paid":null,"fwci":0.9054,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.77622561,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"416","last_page":"421"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.7128439545631409},{"id":"https://openalex.org/keywords/domino-logic","display_name":"Domino logic","score":0.6874597072601318},{"id":"https://openalex.org/keywords/nand-logic","display_name":"NAND logic","score":0.6355770230293274},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6189594864845276},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6102203130722046},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5607565641403198},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5297905802726746},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.5172199010848999},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5148833990097046},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.5141175389289856},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.5067527890205383},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.4559512734413147},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.44777601957321167},{"id":"https://openalex.org/keywords/nor-gate","display_name":"NOR gate","score":0.43588489294052124},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4283349812030792},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4209754467010498},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4177710711956024},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3239036798477173},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2660405933856964},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2655044496059418},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.26262015104293823},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.13102614879608154}],"concepts":[{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.7128439545631409},{"id":"https://openalex.org/C2777555262","wikidata":"https://www.wikidata.org/wiki/Q173391","display_name":"Domino logic","level":5,"score":0.6874597072601318},{"id":"https://openalex.org/C7234692","wikidata":"https://www.wikidata.org/wiki/Q4116068","display_name":"NAND logic","level":4,"score":0.6355770230293274},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6189594864845276},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6102203130722046},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5607565641403198},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5297905802726746},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.5172199010848999},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5148833990097046},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.5141175389289856},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.5067527890205383},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.4559512734413147},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.44777601957321167},{"id":"https://openalex.org/C126445297","wikidata":"https://www.wikidata.org/wiki/Q8065380","display_name":"NOR gate","level":4,"score":0.43588489294052124},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4283349812030792},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4209754467010498},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4177710711956024},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3239036798477173},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2660405933856964},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2655044496059418},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.26262015104293823},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.13102614879608154},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1127908.1128003","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1127908.1128003","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 16th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.7400000095367432}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W270615609","https://openalex.org/W1969097534","https://openalex.org/W2075079194","https://openalex.org/W2083124406","https://openalex.org/W2134849712","https://openalex.org/W2149743155","https://openalex.org/W2166874959"],"related_works":["https://openalex.org/W188762367","https://openalex.org/W1017999001","https://openalex.org/W4361799621","https://openalex.org/W2565020286","https://openalex.org/W2279974209","https://openalex.org/W4252993849","https://openalex.org/W2355985656","https://openalex.org/W2343786151","https://openalex.org/W2893550433","https://openalex.org/W2789662562"],"abstract_inverted_index":{"The":[0,25,43,55],"design":[1],"of":[2,18,32],"programmable":[3],"logic":[4,14],"arrays":[5],"using":[6],"NAND-NOR":[7],"gates":[8,37],"for":[9,50],"the":[10,19,40],"AND":[11,41,88],"and":[12,53,61,92],"OR":[13,44],"planes,":[15],"respectively,":[16],"instead":[17],"conventional":[20],"NOR-NOR":[21],"planes":[22],"is":[23,46],"described.":[24,65],"circuit":[26],"architecture":[27],"uses":[28],"a":[29,68],"hierarchical":[30],"tree":[31],"four":[33],"input":[34],"domino":[35],"NAND":[36],"to":[38,86],"implement":[39],"plane.":[42],"plane":[45,89],"split":[47],"in":[48],"two":[49],"increased":[51],"speed":[52],"robustness.":[54],"circuits":[56],"as":[57,59],"well":[58],"timing":[60],"power":[62,76],"advantages":[63],"are":[64],"Simulations":[66],"on":[67],"foundry":[69],"130":[70],"nm":[71],"process":[72],"show":[73],"nearly":[74],"50%":[75],"savings":[77],"at":[78],"less":[79],"than":[80],"10%":[81],"delay":[82],"cost,":[83],"primarily":[84],"due":[85],"lower":[87],"activity":[90],"factor":[91],"reduced":[93],"clock":[94],"loading.":[95]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}