{"id":"https://openalex.org/W2152638072","doi":"https://doi.org/10.1145/1127908.1127948","title":"Effects of process and environmental variations on timing characteristics of clocked registers","display_name":"Effects of process and environmental variations on timing characteristics of clocked registers","publication_year":2006,"publication_date":"2006-04-30","ids":{"openalex":"https://openalex.org/W2152638072","doi":"https://doi.org/10.1145/1127908.1127948","mag":"2152638072"},"language":"en","primary_location":{"id":"doi:10.1145/1127908.1127948","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1127908.1127948","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 16th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109158309","display_name":"W. Roberts","orcid":null},"institutions":[{"id":"https://openalex.org/I180949307","display_name":"Illinois Institute of Technology","ror":"https://ror.org/037t3ry66","country_code":"US","type":"education","lineage":["https://openalex.org/I180949307"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"William R. Roberts","raw_affiliation_strings":["Illinois Institute of Technology, Chicago, IL"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Illinois Institute of Technology, Chicago, IL","institution_ids":["https://openalex.org/I180949307"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5050757937","display_name":"Dimitrios Velenis","orcid":"https://orcid.org/0000-0001-7947-8098"},"institutions":[{"id":"https://openalex.org/I180949307","display_name":"Illinois Institute of Technology","ror":"https://ror.org/037t3ry66","country_code":"US","type":"education","lineage":["https://openalex.org/I180949307"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dimitrios Velenis","raw_affiliation_strings":["Illinois Institute of Technology, Chicago, IL"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Illinois Institute of Technology, Chicago, IL","institution_ids":["https://openalex.org/I180949307"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.7669,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.76247532,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"165","last_page":"168"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.7131606936454773},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.7035766839981079},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6090281009674072},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.5695812106132507},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5231224894523621},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.5078473687171936},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5025427341461182},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4835767149925232},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.471745103597641},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4182559847831726},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.23911955952644348},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19214749336242676},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.18644371628761292},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.11383667588233948},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.091511070728302},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.07344558835029602}],"concepts":[{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.7131606936454773},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.7035766839981079},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6090281009674072},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.5695812106132507},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5231224894523621},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.5078473687171936},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5025427341461182},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4835767149925232},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.471745103597641},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4182559847831726},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.23911955952644348},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19214749336242676},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.18644371628761292},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.11383667588233948},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.091511070728302},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.07344558835029602},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1127908.1127948","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1127908.1127948","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 16th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1508860734","https://openalex.org/W1875554762","https://openalex.org/W2019198721","https://openalex.org/W2066343858","https://openalex.org/W2097884286","https://openalex.org/W2109195618","https://openalex.org/W2120094593","https://openalex.org/W2133295215","https://openalex.org/W2137616964","https://openalex.org/W2153903472","https://openalex.org/W4238068322"],"related_works":["https://openalex.org/W4229446324","https://openalex.org/W2158805860","https://openalex.org/W3151506308","https://openalex.org/W2110367374","https://openalex.org/W2160859600","https://openalex.org/W3092420867","https://openalex.org/W2115729972","https://openalex.org/W2042032654","https://openalex.org/W2158291854","https://openalex.org/W2769457990"],"abstract_inverted_index":{"Violations":[0],"of":[1,18,25,39,74],"the":[2,22,29,40,72],"timing":[3,23,30],"constraints":[4,31],"in":[5,34,49],"a":[6,11],"clocked":[7],"register":[8,63,76],"can":[9],"cause":[10],"synchronous":[12],"system":[13],"to":[14,47,77],"malfunction.":[15],"The":[16,37],"effects":[17],"parameter":[19],"variations":[20,48],"on":[21],"characteristics":[24],"registers":[26],"that":[27,70],"determine":[28],"are":[32,68],"investigated":[33],"this":[35],"paper.":[36],"sensitivity":[38],"setup":[41],"time":[42],"and":[43,54],"data":[44],"propagation":[45],"delay":[46],"power":[50],"supply":[51],"voltage,":[52],"temperature,":[53],"gate":[55],"oxide":[56],"thickness":[57],"is":[58],"demonstrated":[59],"for":[60],"four":[61],"different":[62],"designs.":[64],"Furthermore,":[65],"design":[66],"modifications":[67],"proposed":[69],"enhance":[71],"robustness":[73],"each":[75],"variation":[78],"effects.":[79]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}