{"id":"https://openalex.org/W2118353886","doi":"https://doi.org/10.1145/1127908.1127947","title":"Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology","display_name":"Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology","publication_year":2006,"publication_date":"2006-04-30","ids":{"openalex":"https://openalex.org/W2118353886","doi":"https://doi.org/10.1145/1127908.1127947","mag":"2118353886"},"language":"en","primary_location":{"id":"doi:10.1145/1127908.1127947","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1127908.1127947","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 16th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5009279384","display_name":"Peng Song","orcid":"https://orcid.org/0000-0002-6567-663X"},"institutions":[{"id":"https://openalex.org/I205783295","display_name":"Cornell University","ror":"https://ror.org/05bnh6r87","country_code":"US","type":"education","lineage":["https://openalex.org/I205783295"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Song Peng","raw_affiliation_strings":["Cornell University, Ithaca, NY","Cornell University (Ithaca, NY);"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cornell University, Ithaca, NY","institution_ids":["https://openalex.org/I205783295"]},{"raw_affiliation_string":"Cornell University (Ithaca, NY);","institution_ids":["https://openalex.org/I205783295"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002575415","display_name":"Rajit Manohar","orcid":"https://orcid.org/0000-0001-8211-6602"},"institutions":[{"id":"https://openalex.org/I205783295","display_name":"Cornell University","ror":"https://ror.org/05bnh6r87","country_code":"US","type":"education","lineage":["https://openalex.org/I205783295"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rajit Manohar","raw_affiliation_strings":["Cornell University, Ithaca, NY","Cornell University (Ithaca, NY);"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cornell University, Ithaca, NY","institution_ids":["https://openalex.org/I205783295"]},{"raw_affiliation_string":"Cornell University (Ithaca, NY);","institution_ids":["https://openalex.org/I205783295"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I205783295"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.14839424,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"159","last_page":"164"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7401182651519775},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.7389364838600159},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.683983564376831},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6106239557266235},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5760242938995361},{"id":"https://openalex.org/keywords/spare-part","display_name":"Spare part","score":0.562998354434967},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5540758371353149},{"id":"https://openalex.org/keywords/planar","display_name":"Planar","score":0.5150806307792664},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5149856209754944},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4448850750923157},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.43911847472190857},{"id":"https://openalex.org/keywords/yield","display_name":"Yield (engineering)","score":0.437541127204895},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.4353233575820923},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.4224146008491516},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.30784326791763306},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.23864147067070007},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23738303780555725},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.18726906180381775},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.17899233102798462},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.14522069692611694},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09930622577667236},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.08143600821495056},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.08128881454467773}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7401182651519775},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.7389364838600159},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.683983564376831},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6106239557266235},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5760242938995361},{"id":"https://openalex.org/C194648553","wikidata":"https://www.wikidata.org/wiki/Q1364774","display_name":"Spare part","level":2,"score":0.562998354434967},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5540758371353149},{"id":"https://openalex.org/C134786449","wikidata":"https://www.wikidata.org/wiki/Q3391255","display_name":"Planar","level":2,"score":0.5150806307792664},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5149856209754944},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4448850750923157},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43911847472190857},{"id":"https://openalex.org/C134121241","wikidata":"https://www.wikidata.org/wiki/Q899301","display_name":"Yield (engineering)","level":2,"score":0.437541127204895},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.4353233575820923},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.4224146008491516},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.30784326791763306},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.23864147067070007},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23738303780555725},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.18726906180381775},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.17899233102798462},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.14522069692611694},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09930622577667236},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.08143600821495056},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.08128881454467773},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C191897082","wikidata":"https://www.wikidata.org/wiki/Q11467","display_name":"Metallurgy","level":1,"score":0.0},{"id":"https://openalex.org/C121684516","wikidata":"https://www.wikidata.org/wiki/Q7600677","display_name":"Computer graphics (images)","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1127908.1127947","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1127908.1127947","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 16th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.139.3958","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.139.3958","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://vlsi.cornell.edu/~rajit/ps/yield3d.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.4300000071525574,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W16511050","https://openalex.org/W1533299367","https://openalex.org/W1549605189","https://openalex.org/W2029709329","https://openalex.org/W2059456074","https://openalex.org/W2106780604","https://openalex.org/W2110709744","https://openalex.org/W2116775565","https://openalex.org/W2124672146","https://openalex.org/W2130175912","https://openalex.org/W2131086257","https://openalex.org/W2144149750","https://openalex.org/W2151335319","https://openalex.org/W2151913116","https://openalex.org/W4236743822"],"related_works":["https://openalex.org/W2072840391","https://openalex.org/W818963952","https://openalex.org/W1939541994","https://openalex.org/W2039140951","https://openalex.org/W1592424226","https://openalex.org/W2157277696","https://openalex.org/W2018106661","https://openalex.org/W2166402441","https://openalex.org/W2125277664","https://openalex.org/W4240821575"],"abstract_inverted_index":{"This":[0,86],"paper":[1],"presents":[2],"a":[3],"systematic":[4],"design":[5,87],"for":[6],"yield":[7,73,84],"enhancement":[8],"of":[9,69],"asynchronous":[10,23],"logic":[11,54],"circuits":[12,24],"using":[13],"3-D":[14],"(3-Dimensional)":[15],"integration":[16],"technology.":[17],"In":[18],"this":[19,77],"design,":[20],"the":[21,67],"target":[22],"on":[25,38,55],"one":[26],"planar":[27,57],"device":[28,58],"layer":[29,59],"which":[30,60],"is":[31,61],"fabricated":[32,62],"with":[33,43,63],"aggressive":[34],"technology,":[35,65],"are":[36],"built":[37],"fault":[39],"tolerant":[40],"graph":[41],"models":[42],"extra":[44],"spare":[45],"resources,":[46],"and":[47],"can":[48,79,89],"be":[49,90],"reconfigured":[50],"by":[51],"autonomous":[52],"reconfiguration":[53],"another":[56],"conservative":[64],"in":[66,81],"presence":[68],"hard":[70],"errors.":[71],"The":[72],"analysis":[74],"shows":[75],"that":[76],"method":[78],"result":[80],"20--30%":[82],"overall":[83],"enhancement.":[85],"methodology":[88],"conveniently":[91],"applied":[92],"to":[93],"clocked":[94],"designs":[95],"without":[96],"significant":[97],"changes.":[98]},"counts_by_year":[],"updated_date":"2026-08-26T07:47:46.906454","created_date":"2025-10-10T00:00:00"}