{"id":"https://openalex.org/W1985714852","doi":"https://doi.org/10.1145/1123008.1123026","title":"Floorplan and power/ground network co-synthesis for fast design convergence","display_name":"Floorplan and power/ground network co-synthesis for fast design convergence","publication_year":2006,"publication_date":"2006-04-09","ids":{"openalex":"https://openalex.org/W1985714852","doi":"https://doi.org/10.1145/1123008.1123026","mag":"1985714852"},"language":"en","primary_location":{"id":"doi:10.1145/1123008.1123026","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1123008.1123026","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2006 international symposium on Physical design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103162448","display_name":"Chen\u2010Wei Liu","orcid":"https://orcid.org/0000-0003-2826-465X"},"institutions":[{"id":"https://openalex.org/I1335490905","display_name":"Synopsys (Switzerland)","ror":"https://ror.org/03mb54f81","country_code":"CH","type":"company","lineage":["https://openalex.org/I1335490905","https://openalex.org/I4210088951"]}],"countries":["CH"],"is_corresponding":true,"raw_author_name":"Chen-Wei Liu","raw_affiliation_strings":["Synopsys Taiwan Limited, Taipei, Taiwan","Synopsys Taiwan Limited, Taipei, Taiwan#TAB#"],"affiliations":[{"raw_affiliation_string":"Synopsys Taiwan Limited, Taipei, Taiwan","institution_ids":[]},{"raw_affiliation_string":"Synopsys Taiwan Limited, Taipei, Taiwan#TAB#","institution_ids":["https://openalex.org/I1335490905"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018371636","display_name":"Yao\u2010Wen Chang","orcid":"https://orcid.org/0000-0002-0564-5719"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yao-Wen Chang","raw_affiliation_strings":["National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5103162448"],"corresponding_institution_ids":["https://openalex.org/I1335490905"],"apc_list":null,"apc_paid":null,"fwci":4.2124,"has_fulltext":false,"cited_by_count":24,"citation_normalized_percentile":{"value":0.93575001,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"86","last_page":"93"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.9849348068237305},{"id":"https://openalex.org/keywords/power-network-design","display_name":"Power network design","score":0.791845440864563},{"id":"https://openalex.org/keywords/power-integrity","display_name":"Power integrity","score":0.7178542613983154},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5719218850135803},{"id":"https://openalex.org/keywords/convergence","display_name":"Convergence (economics)","score":0.5141823291778564},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.5051601529121399},{"id":"https://openalex.org/keywords/voltage-drop","display_name":"Voltage drop","score":0.50105881690979},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.49529901146888733},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.47500574588775635},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.457985520362854},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.43867671489715576},{"id":"https://openalex.org/keywords/network-planning-and-design","display_name":"Network planning and design","score":0.43842896819114685},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4170208275318146},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.3176169991493225},{"id":"https://openalex.org/keywords/signal-integrity","display_name":"Signal integrity","score":0.24638283252716064},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23321503400802612},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.1933474838733673},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.16995567083358765},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.11755532026290894},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0824035108089447}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.9849348068237305},{"id":"https://openalex.org/C164565468","wikidata":"https://www.wikidata.org/wiki/Q7236535","display_name":"Power network design","level":3,"score":0.791845440864563},{"id":"https://openalex.org/C2777561913","wikidata":"https://www.wikidata.org/wiki/Q19599527","display_name":"Power integrity","level":4,"score":0.7178542613983154},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5719218850135803},{"id":"https://openalex.org/C2777303404","wikidata":"https://www.wikidata.org/wiki/Q759757","display_name":"Convergence (economics)","level":2,"score":0.5141823291778564},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.5051601529121399},{"id":"https://openalex.org/C82178898","wikidata":"https://www.wikidata.org/wiki/Q166839","display_name":"Voltage drop","level":3,"score":0.50105881690979},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.49529901146888733},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.47500574588775635},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.457985520362854},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.43867671489715576},{"id":"https://openalex.org/C114563136","wikidata":"https://www.wikidata.org/wiki/Q19725982","display_name":"Network planning and design","level":2,"score":0.43842896819114685},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4170208275318146},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.3176169991493225},{"id":"https://openalex.org/C44938667","wikidata":"https://www.wikidata.org/wiki/Q4503810","display_name":"Signal integrity","level":3,"score":0.24638283252716064},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23321503400802612},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.1933474838733673},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.16995567083358765},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.11755532026290894},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0824035108089447},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1123008.1123026","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1123008.1123026","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2006 international symposium on Physical design","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.135.3872","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.135.3872","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://cc.ee.ntu.edu.tw/~ywchang/Papers/ispd06-pg.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W72355807","https://openalex.org/W2002603101","https://openalex.org/W2014073941","https://openalex.org/W2014489057","https://openalex.org/W2021998347","https://openalex.org/W2065120607","https://openalex.org/W2100740271","https://openalex.org/W2105074558","https://openalex.org/W2109258578","https://openalex.org/W2131254145","https://openalex.org/W2138263555","https://openalex.org/W2148777220","https://openalex.org/W2153069345","https://openalex.org/W2155571529","https://openalex.org/W2171236961","https://openalex.org/W2752885492","https://openalex.org/W2798909945","https://openalex.org/W3145128584"],"related_works":["https://openalex.org/W4386632162","https://openalex.org/W2171236961","https://openalex.org/W4256630426","https://openalex.org/W2133492470","https://openalex.org/W1985714852","https://openalex.org/W2014223528","https://openalex.org/W2533759086","https://openalex.org/W2246813539","https://openalex.org/W2155412769","https://openalex.org/W2097839191"],"abstract_inverted_index":{"As":[0],"technology":[1],"advances,":[2],"the":[3,8,16,19,25,31,34,38,43,48,83,131,137,163,173,178,184],"metal":[4],"width":[5],"decreases":[6],"while":[7],"global":[9],"wire":[10,21],"length":[11],"increases.":[12],"This":[13],"trend":[14],"makes":[15],"resistance":[17],"of":[18,33],"power":[20,148],"increase":[22],"substantially.":[23],"Further,":[24],"threshold":[26,35],"voltage":[27,36,40,44],"scales":[28],"nonlinearly,":[29],"raising":[30],"ratio":[32],"to":[37,75,144],"supply":[39],"and":[41,69,93,118,130,162,181],"making":[42],"(IR)":[45],"drop":[46],"in":[47,55],"power/ground":[49],"(P/G)":[50],"network":[51,61,78,106,120,127],"a":[52,99,114,140,158],"serious":[53],"problem":[54],"modern":[56],"IC":[57],"design.":[58],"Traditional":[59],"P/G":[60,77,105,119,126],"analysis":[62,107,128],"methods":[63],"are":[64],"often":[65],"very":[66,100],"computationally":[67],"expensive,":[68],"it":[70],"is":[71],"thus":[72,182],"not":[73,88],"feasible":[74],"co-synthesize":[76],"with":[79],"floorplan.":[80],"To":[81],"make":[82],"co-synthesis":[84,121,138],"feasible,":[85],"we":[86,112],"need":[87],"only":[89],"an":[90,124,146],"efficient,":[91,101],"effective,":[92],"flexible":[94],"floorplanning":[95,179],"algorithm,":[96],"but":[97],"also":[98],"yet":[102],"sufficiently":[103],"accurate":[104],"method.":[108],"In":[109],"this":[110],"paper,":[111],"present":[113],"method":[115],"for":[116],"floorplan":[117,133],"based":[122,156],"on":[123,157],"efficient":[125],"scheme":[129],"B*-tree":[132],"representation.":[134],"We":[135],"integrate":[136],"into":[139],"commercial":[141],"design":[142,152,161,169,186],"flow":[143],"develop":[145],"effective":[147],"integrity":[149],"(IR-drop)":[150],"driven":[151],"methodology.":[153],"Experimental":[154],"results":[155],"real-world":[159],"circuit":[160],"MCNC":[164],"benchmarks":[165],"show":[166],"that":[167],"our":[168],"methodology":[170],"successfully":[171],"fixes":[172],"IR-drop":[174],"errors":[175],"earlier":[176],"at":[177],"stage":[180],"enables":[183],"single-pass":[185],"convergence.":[187]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}