{"id":"https://openalex.org/W2018131538","doi":"https://doi.org/10.1145/1120725.1120976","title":"IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems","display_name":"IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems","publication_year":2005,"publication_date":"2005-01-01","ids":{"openalex":"https://openalex.org/W2018131538","doi":"https://doi.org/10.1145/1120725.1120976","mag":"2018131538"},"language":"en","primary_location":{"id":"doi:10.1145/1120725.1120976","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1120725.1120976","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 conference on Asia South Pacific design automation  - ASP-DAC '05","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109240766","display_name":"Nacer-Eddine Zergainoh","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Nacer-Eddine Zergainoh","raw_affiliation_strings":["TIMA Laboratory, Grenoble, France","SLS group, TIMA Lab., Grenoble, France"],"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]},{"raw_affiliation_string":"SLS group, TIMA Lab., Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054779458","display_name":"Katalin Popovici","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Katalin Popovici","raw_affiliation_strings":["TIMA Laboratory, Grenoble, France","SLS group, TIMA Lab., Grenoble, France"],"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]},{"raw_affiliation_string":"SLS group, TIMA Lab., Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113780350","display_name":"Ahmed Jerraya","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Ahmed Jerraya","raw_affiliation_strings":["TIMA Laboratory, Grenoble, France","SLS group, TIMA Lab., Grenoble, France"],"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]},{"raw_affiliation_string":"SLS group, TIMA Lab., Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111440581","display_name":"Pascal Urard","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104693","display_name":"STMicroelectronics (France)","ror":"https://ror.org/01c74sd89","country_code":"FR","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]},{"id":"https://openalex.org/I131827901","display_name":"STMicroelectronics (Switzerland)","ror":"https://ror.org/00wm3b005","country_code":"CH","type":"company","lineage":["https://openalex.org/I131827901"]}],"countries":["CH","FR"],"is_corresponding":false,"raw_author_name":"Pascal Urard","raw_affiliation_strings":["ST Microelectronics, Crolles, France","ST Microelectronics Crolles France"],"affiliations":[{"raw_affiliation_string":"ST Microelectronics, Crolles, France","institution_ids":["https://openalex.org/I4210104693"]},{"raw_affiliation_string":"ST Microelectronics Crolles France","institution_ids":["https://openalex.org/I131827901"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5109240766"],"corresponding_institution_ids":["https://openalex.org/I4210087012"],"apc_list":null,"apc_paid":null,"fwci":1.0555,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.78238929,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"612","last_page":"612"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.8293646574020386},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7804825305938721},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6759664416313171},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6133887767791748},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.57406085729599},{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.5721948146820068},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5574522018432617},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5550186038017273},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5394514203071594},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.45802104473114014},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.42982104420661926},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.41207700967788696},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.23770445585250854},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08091780543327332}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.8293646574020386},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7804825305938721},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6759664416313171},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6133887767791748},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.57406085729599},{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.5721948146820068},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5574522018432617},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5550186038017273},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5394514203071594},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.45802104473114014},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.42982104420661926},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.41207700967788696},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.23770445585250854},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08091780543327332},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/1120725.1120976","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1120725.1120976","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 conference on Asia South Pacific design automation  - ASP-DAC '05","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.147.1522","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.147.1522","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://tima.imag.fr/sls/documents/Final_asp_dac_zer.pdf","raw_type":"text"},{"id":"pmh:oai:HAL:hal-00008000v1","is_oa":false,"landing_page_url":"https://hal.science/hal-00008000","pdf_url":null,"source":{"id":"https://openalex.org/S4406922461","display_name":"SPIRE - Sciences Po Institutional REpository","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Asia and South Pacific Design Automation Conference (ASP-DAC'05), Jan 2005, Shanghai, China. pp.612-618","raw_type":"Conference papers"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.47999998927116394,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320323512","display_name":"Buddhist Tzu Chi Medical Foundation","ror":"https://ror.org/04rbvc675"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W752039407","https://openalex.org/W1607087175","https://openalex.org/W1884307536","https://openalex.org/W1986698883","https://openalex.org/W2013739734","https://openalex.org/W2040616642","https://openalex.org/W2061341864","https://openalex.org/W2090242529","https://openalex.org/W2099089225","https://openalex.org/W2102386141","https://openalex.org/W2111817123","https://openalex.org/W2115579040","https://openalex.org/W2129940857","https://openalex.org/W2132324656","https://openalex.org/W2139310161","https://openalex.org/W2150301947","https://openalex.org/W2170480266","https://openalex.org/W3152447448"],"related_works":["https://openalex.org/W2752828786","https://openalex.org/W4235515009","https://openalex.org/W2242433395","https://openalex.org/W2544073398","https://openalex.org/W2548514518","https://openalex.org/W2171413119","https://openalex.org/W2579932084","https://openalex.org/W2543290882","https://openalex.org/W1603163876","https://openalex.org/W2133642747"],"abstract_inverted_index":{"The":[0,41,63,94,109],"Growing":[1],"requirement":[2],"on":[3],"the":[4,75,88,106,113],"correct":[5],"design":[6,34],"of":[7,60,77,90,125],"a":[8,52,58,83,122],"high":[9,37],"performance":[10],"DSP":[11],"system":[12],"in":[13,21,105],"short":[14],"time":[15],"force":[16],"us":[17],"to":[18,70,86],"use":[19,76],"IP's":[20],"many":[22],"design.":[23],"In":[24],"this":[25],"paper,":[26],"we":[27],"propose":[28],"an":[29],"efficient":[30,117],"IP":[31],"block":[32],"based":[33],"environment":[35],"for":[36],"throughput":[38],"VLSI":[39],"Systems.":[40],"flow":[42],"generates":[43],"SystemC":[44],"Register":[45],"Transfer":[46],"Level":[47],"(RTL)":[48],"architecture,":[49],"starting":[50],"from":[51],"Matlab":[53],"functional":[54,61],"model":[55],"described":[56],"as":[57],"netlist":[59],"IP.":[62,93],"refinement":[64],"process":[65],"inserts":[66,82],"automatically":[67],"control":[68,84,107],"structures":[69],"treat":[71],"delays":[72,95],"induced":[73],"by":[74,99,102],"RTL":[78,118],"IPs.":[79],"It":[80],"also":[81],"structure":[85],"coordinate":[87],"execution":[89],"parallel":[91],"clocked":[92],"may":[96],"be":[97],"managed":[98],"registers":[100],"or":[101],"counters":[103],"included":[104],"structure.":[108],"experimentations":[110],"show":[111],"that":[112],"approach":[114],"can":[115],"produce":[116],"architecture":[119],"and":[120],"allow":[121],"huge":[123],"save":[124],"time.":[126]},"counts_by_year":[{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
