{"id":"https://openalex.org/W2115602380","doi":"https://doi.org/10.1145/1120725.1120929","title":"Timing driven track routing considering coupling capacitance","display_name":"Timing driven track routing considering coupling capacitance","publication_year":2005,"publication_date":"2005-01-01","ids":{"openalex":"https://openalex.org/W2115602380","doi":"https://doi.org/10.1145/1120725.1120929","mag":"2115602380"},"language":"en","primary_location":{"id":"doi:10.1145/1120725.1120929","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1120725.1120929","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 conference on Asia South Pacific design automation  - ASP-DAC '05","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5104384770","display_name":"Di Wu","orcid":"https://orcid.org/0000-0002-5659-3349"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Di Wu","raw_affiliation_strings":["Texas A&M University, College Station, TX","Texas A&M University, College Station. TX#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas A&M University, College Station, TX","institution_ids":["https://openalex.org/I91045830"]},{"raw_affiliation_string":"Texas A&M University, College Station. TX#TAB#","institution_ids":["https://openalex.org/I91045830"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103246390","display_name":"Jiang Hu","orcid":"https://orcid.org/0000-0003-1157-7799"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jiang Hu","raw_affiliation_strings":["Texas A&M University, College Station, TX","Texas A&M University, College Station. TX#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas A&M University, College Station, TX","institution_ids":["https://openalex.org/I91045830"]},{"raw_affiliation_string":"Texas A&M University, College Station. TX#TAB#","institution_ids":["https://openalex.org/I91045830"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101784756","display_name":"Min Zhao","orcid":"https://orcid.org/0000-0003-0553-5146"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Min Zhao","raw_affiliation_strings":["Freescale Semiconductor, Austin, TX"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor, Austin, TX","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103702897","display_name":"Rabi Mahapatra","orcid":"https://orcid.org/0000-0003-1702-8045"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rabi Mahapatra","raw_affiliation_strings":["Texas A&M University, College Station, TX","Texas A&M University, College Station. TX#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas A&M University, College Station, TX","institution_ids":["https://openalex.org/I91045830"]},{"raw_affiliation_string":"Texas A&M University, College Station. TX#TAB#","institution_ids":["https://openalex.org/I91045830"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.9074,"has_fulltext":false,"cited_by_count":23,"citation_normalized_percentile":{"value":0.9089385,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1156","last_page":"1156"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.8183085322380066},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7394525408744812},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6402289271354675},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5736436247825623},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5708853602409363},{"id":"https://openalex.org/keywords/coupling","display_name":"Coupling (piping)","score":0.5599342584609985},{"id":"https://openalex.org/keywords/equal-cost-multi-path-routing","display_name":"Equal-cost multi-path routing","score":0.5383466482162476},{"id":"https://openalex.org/keywords/heuristic","display_name":"Heuristic","score":0.5089497566223145},{"id":"https://openalex.org/keywords/place-and-route","display_name":"Place and route","score":0.4227887690067291},{"id":"https://openalex.org/keywords/multipath-routing","display_name":"Multipath routing","score":0.4184891879558563},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.41116905212402344},{"id":"https://openalex.org/keywords/static-routing","display_name":"Static routing","score":0.38485977053642273},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3657827377319336},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.35810357332229614},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3562983572483063},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2274443507194519},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1880260407924652},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.15787604451179504},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.1365875005722046},{"id":"https://openalex.org/keywords/routing-protocol","display_name":"Routing protocol","score":0.10796386003494263}],"concepts":[{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.8183085322380066},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7394525408744812},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6402289271354675},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5736436247825623},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5708853602409363},{"id":"https://openalex.org/C131584629","wikidata":"https://www.wikidata.org/wiki/Q4308705","display_name":"Coupling (piping)","level":2,"score":0.5599342584609985},{"id":"https://openalex.org/C115443555","wikidata":"https://www.wikidata.org/wiki/Q5367790","display_name":"Equal-cost multi-path routing","level":5,"score":0.5383466482162476},{"id":"https://openalex.org/C173801870","wikidata":"https://www.wikidata.org/wiki/Q201413","display_name":"Heuristic","level":2,"score":0.5089497566223145},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.4227887690067291},{"id":"https://openalex.org/C76522221","wikidata":"https://www.wikidata.org/wiki/Q5035396","display_name":"Multipath routing","level":5,"score":0.4184891879558563},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.41116905212402344},{"id":"https://openalex.org/C204948658","wikidata":"https://www.wikidata.org/wiki/Q1119410","display_name":"Static routing","level":4,"score":0.38485977053642273},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3657827377319336},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.35810357332229614},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3562983572483063},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2274443507194519},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1880260407924652},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.15787604451179504},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.1365875005722046},{"id":"https://openalex.org/C104954878","wikidata":"https://www.wikidata.org/wiki/Q1648707","display_name":"Routing protocol","level":3,"score":0.10796386003494263},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/1120725.1120929","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1120725.1120929","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 conference on Asia South Pacific design automation  - ASP-DAC '05","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.534.3175","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.534.3175","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://dropzone.tamu.edu/~jhu/publications/WuASPDAC05.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.89.9882","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.89.9882","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://research.cs.tamu.edu/codesign/papers/aspdac05_TR.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W126325332","https://openalex.org/W2009265617","https://openalex.org/W2023811290","https://openalex.org/W2032145219","https://openalex.org/W2049111024","https://openalex.org/W2098765048","https://openalex.org/W2098864989","https://openalex.org/W2103986692","https://openalex.org/W2112205298","https://openalex.org/W2115734116","https://openalex.org/W2120599026","https://openalex.org/W2121290396","https://openalex.org/W2123728905","https://openalex.org/W2128732569","https://openalex.org/W2129736362","https://openalex.org/W2136728320","https://openalex.org/W2143250861","https://openalex.org/W2159490969","https://openalex.org/W2169531002","https://openalex.org/W2201681339"],"related_works":["https://openalex.org/W2181601090","https://openalex.org/W3127002380","https://openalex.org/W2068473861","https://openalex.org/W757657516","https://openalex.org/W2351878639","https://openalex.org/W2539097916","https://openalex.org/W2136173851","https://openalex.org/W2029407480","https://openalex.org/W4253436398","https://openalex.org/W2556128816"],"abstract_inverted_index":{"As":[0],"VLSI":[1],"technology":[2],"enters":[3],"the":[4,62,117,127],"ultra-deep":[5],"submicron":[6],"era,":[7],"wire":[8,53,78],"coupling":[9,30,75,120,135],"capacitance":[10,15,76,121],"starts":[11],"to":[12,57],"dominate":[13],"self":[14],"and":[16,44,77,92,126],"can":[17],"no":[18],"longer":[19],"be":[20],"neglected":[21],"in":[22,82,104,131],"timing":[23,32,45,64,123,137],"driven":[24,33],"routing.":[25],"In":[26],"this":[27],"paper,":[28],"a":[29,40,83,95,105],"aware":[31,136],"track":[34],"routing":[35,42,58],"heuristic":[36,129],"is":[37,69,90,124],"proposed.":[38],"Given":[39],"global":[41],"solution":[43],"constraint":[46],"for":[47],"each":[48],"net,":[49],"major":[50],"trunks":[51],"of":[52,119],"segments":[54],"are":[55,80,102],"assigned":[56],"tracks":[59],"such":[60],"that":[61,116],"minimum":[63],"slack":[65],"among":[66],"all":[67],"nets":[68],"maximized.":[70],"Delay":[71],"penalties":[72],"from":[73],"both":[74],"detour":[79],"considered":[81],"unified":[84],"graph":[85],"model.":[86],"The":[87,109],"core":[88],"problem":[89],"formulated":[91],"solved":[93],"as":[94],"Sequential":[96],"Ordering":[97],"Problem":[98],"(SOP).":[99],"Routing":[100],"blockages":[101],"handled":[103],"post":[106],"processing":[107],"procedure.":[108],"experimental":[110],"results":[111,130],"on":[112,122,134],"benchmark":[113],"circuits":[114],"show":[115],"effect":[118],"significant":[125],"proposed":[128],"greater":[132],"improvement":[133],"compared":[138],"with":[139],"other":[140],"approaches.":[141]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}