{"id":"https://openalex.org/W2023683184","doi":"https://doi.org/10.1145/1120725.1120894","title":"Design and implementation of an SDH high-speed switch","display_name":"Design and implementation of an SDH high-speed switch","publication_year":2005,"publication_date":"2005-01-01","ids":{"openalex":"https://openalex.org/W2023683184","doi":"https://doi.org/10.1145/1120725.1120894","mag":"2023683184"},"language":"en","primary_location":{"id":"doi:10.1145/1120725.1120894","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1120725.1120894","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 conference on Asia South Pacific design automation  - ASP-DAC '05","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111681243","display_name":"D Zhang","orcid":null},"institutions":[{"id":"https://openalex.org/I4210136859","display_name":"Xi\u2019an University of Posts and Telecommunications","ror":"https://ror.org/04jn0td46","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210136859"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"De_Hui Zhang","raw_affiliation_strings":["Xi'an Institute of Post and Telecommunications, Xi'an, P.R. China","Dept. of Comput. Sci., Xi'an Inst. of Post & Telecommun., China"],"affiliations":[{"raw_affiliation_string":"Xi'an Institute of Post and Telecommunications, Xi'an, P.R. China","institution_ids":["https://openalex.org/I4210136859"]},{"raw_affiliation_string":"Dept. of Comput. Sci., Xi'an Inst. of Post & Telecommun., China","institution_ids":["https://openalex.org/I4210136859"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090566453","display_name":"Quan Liang Zhao","orcid":null},"institutions":[{"id":"https://openalex.org/I4210136859","display_name":"Xi\u2019an University of Posts and Telecommunications","ror":"https://ror.org/04jn0td46","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210136859"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Quan_Liang Zhao","raw_affiliation_strings":["Xi'an Institute of Post and Telecommunications, Xi'an, P.R. China","Dept. of Comput. Sci., Xi'an Inst. of Post & Telecommun., China"],"affiliations":[{"raw_affiliation_string":"Xi'an Institute of Post and Telecommunications, Xi'an, P.R. China","institution_ids":["https://openalex.org/I4210136859"]},{"raw_affiliation_string":"Dept. of Comput. Sci., Xi'an Inst. of Post & Telecommun., China","institution_ids":["https://openalex.org/I4210136859"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110041751","display_name":"Jun-Gang Han","orcid":null},"institutions":[{"id":"https://openalex.org/I4210136859","display_name":"Xi\u2019an University of Posts and Telecommunications","ror":"https://ror.org/04jn0td46","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210136859"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jun-Gang Han","raw_affiliation_strings":["Xi'an Institute of Post and Telecommunications, Xi'an, P.R. China","Dept. of Comput. Sci., Xi'an Inst. of Post & Telecommun., China"],"affiliations":[{"raw_affiliation_string":"Xi'an Institute of Post and Telecommunications, Xi'an, P.R. China","institution_ids":["https://openalex.org/I4210136859"]},{"raw_affiliation_string":"Dept. of Comput. Sci., Xi'an Inst. of Post & Telecommun., China","institution_ids":["https://openalex.org/I4210136859"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5111681243"],"corresponding_institution_ids":["https://openalex.org/I4210136859"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.13095238,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"17","last_page":"17"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9794999957084656,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9794999957084656,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9753000140190125,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9153000116348267,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7407267689704895},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.670331597328186},{"id":"https://openalex.org/keywords/gigabit","display_name":"Gigabit","score":0.5614282488822937},{"id":"https://openalex.org/keywords/blocking","display_name":"Blocking (statistics)","score":0.5541717410087585},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.524647057056427},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5083019137382507},{"id":"https://openalex.org/keywords/crossover-switch","display_name":"Crossover switch","score":0.47513845562934875},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.3003309965133667},{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.3001939654350281},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0980508029460907}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7407267689704895},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.670331597328186},{"id":"https://openalex.org/C21922175","wikidata":"https://www.wikidata.org/wiki/Q3105497","display_name":"Gigabit","level":2,"score":0.5614282488822937},{"id":"https://openalex.org/C144745244","wikidata":"https://www.wikidata.org/wiki/Q4927286","display_name":"Blocking (statistics)","level":2,"score":0.5541717410087585},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.524647057056427},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5083019137382507},{"id":"https://openalex.org/C12334850","wikidata":"https://www.wikidata.org/wiki/Q1535092","display_name":"Crossover switch","level":3,"score":0.47513845562934875},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.3003309965133667},{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.3001939654350281},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0980508029460907}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1120725.1120894","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1120725.1120894","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 conference on Asia South Pacific design automation  - ASP-DAC '05","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6800000071525574}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2149741868","https://openalex.org/W2136926481","https://openalex.org/W3003518888","https://openalex.org/W2228130850","https://openalex.org/W2022979333","https://openalex.org/W2150160187","https://openalex.org/W2667344013","https://openalex.org/W1983415008","https://openalex.org/W1546580292","https://openalex.org/W2125186498"],"abstract_inverted_index":{"In":[0,23],"this":[1,24],"shot":[2],"paper,":[3],"we":[4],"propose":[5],"a":[6,26],"design":[7,25,54],"of":[8,36,42,52],"SDH":[9],"High-Speed":[10],"Switch,":[11],"which":[12],"can":[13],"switch":[14],"16x16":[15],"STM-16":[16,45],"streams":[17],"with":[18],"speed":[19],"at":[20,48],"2.488":[21],"Gbit/s.":[22],"novel":[27],"fabric":[28],"structure":[29],"was":[30],"used":[31],"to":[32],"perform":[33],"non-blocking":[34],"connection":[35],"STM-1":[37],"data":[38,46],"in":[39,57],"any":[40],"timeslot":[41],"16-bit":[43],"parallel":[44],"rate":[47],"155.5MB/s.":[49],"The":[50,63],"prototype":[51,69],"the":[53,68],"is":[55],"implemented":[56],"Altera's":[58],"StratixTM":[59],"GX":[60],"FPGA":[61],"devices.":[62],"test":[64],"results":[65],"show":[66],"that":[67],"meets":[70],"all":[71],"requirements.":[72]},"counts_by_year":[{"year":2014,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}