{"id":"https://openalex.org/W2121098912","doi":"https://doi.org/10.1145/1120725.1120879","title":"Microarchitecture evaluation with floorplanning and interconnect pipelining","display_name":"Microarchitecture evaluation with floorplanning and interconnect pipelining","publication_year":2005,"publication_date":"2005-01-01","ids":{"openalex":"https://openalex.org/W2121098912","doi":"https://doi.org/10.1145/1120725.1120879","mag":"2121098912"},"language":"en","primary_location":{"id":"doi:10.1145/1120725.1120879","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1120725.1120879","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 conference on Asia South Pacific design automation  - ASP-DAC '05","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038226209","display_name":"Ashok Jagannathan","orcid":null},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ashok Jagannathan","raw_affiliation_strings":["Univ. of California, Los Angeles, CA","Dept. of comput. Sci., California Univ., Los Angeles, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Univ. of California, Los Angeles, CA","institution_ids":["https://openalex.org/I161318765"]},{"raw_affiliation_string":"Dept. of comput. Sci., California Univ., Los Angeles, CA, USA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102112058","display_name":"Hannah Honghua Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hannah Honghua Yang","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR","Intel Corporation, Hillsboro, OR#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000203569","display_name":"Kris Konigsfeld","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kris Konigsfeld","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR","Intel Corporation, Hillsboro, OR#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025030334","display_name":"Dan Milliron","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dan Milliron","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR","Intel Corporation, Hillsboro, OR#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037758981","display_name":"M. Mohan","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mosur Mohan","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR","Intel Corporation, Hillsboro, OR#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075435628","display_name":"Michail Romesis","orcid":null},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michail Romesis","raw_affiliation_strings":["Univ. of California, Los Angeles, CA","University of California, Los Angeles. CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Univ. of California, Los Angeles, CA","institution_ids":["https://openalex.org/I161318765"]},{"raw_affiliation_string":"University of California, Los Angeles. CA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083493225","display_name":"Glenn Reinman","orcid":null},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Glenn Reinman","raw_affiliation_strings":["Univ. of California, Los Angeles, CA","University of California, Los Angeles. CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Univ. of California, Los Angeles, CA","institution_ids":["https://openalex.org/I161318765"]},{"raw_affiliation_string":"University of California, Los Angeles. CA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102170602","display_name":"Jason Cong","orcid":null},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jason Cong","raw_affiliation_strings":["Univ. of California, Los Angeles, CA","University of California, Los Angeles. CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Univ. of California, Los Angeles, CA","institution_ids":["https://openalex.org/I161318765"]},{"raw_affiliation_string":"University of California, Los Angeles. CA","institution_ids":["https://openalex.org/I161318765"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":6.1783,"has_fulltext":false,"cited_by_count":22,"citation_normalized_percentile":{"value":0.96509984,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"8","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/software-pipelining","display_name":"Software pipelining","score":0.7945226430892944},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7747448682785034},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.7459232211112976},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.7256254553794861},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7046855688095093},{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.6035023927688599},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5644122362136841},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5500376224517822},{"id":"https://openalex.org/keywords/superscalar","display_name":"Superscalar","score":0.5351781249046326},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5252810716629028},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4758993089199066},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.44899338483810425},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.43373316526412964},{"id":"https://openalex.org/keywords/low-latency","display_name":"Low latency (capital markets)","score":0.42773330211639404},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4173157811164856},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.14095255732536316},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08742478489875793}],"concepts":[{"id":"https://openalex.org/C188854837","wikidata":"https://www.wikidata.org/wiki/Q268469","display_name":"Software pipelining","level":3,"score":0.7945226430892944},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7747448682785034},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.7459232211112976},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.7256254553794861},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7046855688095093},{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.6035023927688599},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5644122362136841},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5500376224517822},{"id":"https://openalex.org/C147101560","wikidata":"https://www.wikidata.org/wiki/Q1045706","display_name":"Superscalar","level":2,"score":0.5351781249046326},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5252810716629028},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4758993089199066},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.44899338483810425},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.43373316526412964},{"id":"https://openalex.org/C46637626","wikidata":"https://www.wikidata.org/wiki/Q6693015","display_name":"Low latency (capital markets)","level":2,"score":0.42773330211639404},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4173157811164856},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.14095255732536316},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08742478489875793},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1120725.1120879","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1120725.1120879","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 conference on Asia South Pacific design automation  - ASP-DAC '05","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Sustainable cities and communities","id":"https://metadata.un.org/sdg/11","score":0.46000000834465027}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W63944998","https://openalex.org/W1975134759","https://openalex.org/W1983250183","https://openalex.org/W2024060531","https://openalex.org/W2032094184","https://openalex.org/W2096365807","https://openalex.org/W2106270437","https://openalex.org/W2109059344","https://openalex.org/W2111880608","https://openalex.org/W2120062652","https://openalex.org/W2121050483","https://openalex.org/W2123859688","https://openalex.org/W2129760904","https://openalex.org/W2133642820","https://openalex.org/W2140915279","https://openalex.org/W2144249008","https://openalex.org/W2147602666","https://openalex.org/W2150073849","https://openalex.org/W2150369487","https://openalex.org/W2153456949","https://openalex.org/W2154462472","https://openalex.org/W2161864047","https://openalex.org/W2171825402","https://openalex.org/W2489328233"],"related_works":["https://openalex.org/W1521960115","https://openalex.org/W2151851440","https://openalex.org/W2474385219","https://openalex.org/W2230270457","https://openalex.org/W613182605","https://openalex.org/W2544364117","https://openalex.org/W2145523143","https://openalex.org/W3148881121","https://openalex.org/W2078100540","https://openalex.org/W4234722261"],"abstract_inverted_index":{"As":[0],"microprocessor":[1],"technology":[2],"continues":[3],"to":[4,29,40,53,102,119,156],"scale":[5],"into":[6],"the":[7,34,44,47,70,121,147,161,164,168,172],"nanometer":[8],"regime,":[9],"recent":[10],"studies":[11],"show":[12,140],"that":[13,141],"interconnect":[14,81,132,143],"delay":[15],"will":[16,26],"be":[17,27,41,54],"a":[18,74,84,117,134,151],"limiting":[19],"factor":[20],"for":[21,113],"performance,":[22],"and":[23,43,68,110],"multiple":[24],"cycles":[25],"necessary":[28],"communicate":[30],"global":[31],"signals":[32],"across":[33],"chip.":[35],"Thus,":[36],"longer":[37],"interconnects":[38],"need":[39],"pipelined,":[42],"impact":[45,122],"of":[46,97,123,131,163,171],"extra":[48],"latency":[49],"along":[50],"wires":[51],"needs":[52],"considered":[55],"during":[56,107],"early":[57],"micro-architecture":[58,77,98,127,136],"design":[59,137],"exploration.":[60],"In":[61],"this":[62,66],"paper,":[63],"we":[64,139],"address":[65],"problem":[67],"make":[69],"following":[71],"contributions:":[72],"(1)":[73],"oor":[75,108],"plan-driven":[76],"evaluation":[78],"methodology":[79,118,165],"considering":[80,142],"pipelining":[82,144],"at":[83],"given":[85],"target":[86,169],"frequency":[87,124,170],"by":[88],"selectively":[89],"optimizing":[90],"architecture":[91],"level":[92],"critical":[93,105],"paths.":[94],"(2)":[95],"use":[96],"performance":[99,128,149],"sensitivity":[100],"models":[101],"weight":[103],"micro-architectural":[104],"paths":[106],"planning":[109],"optimize":[111],"them":[112],"higher":[114],"performance.":[115],"(3)":[116],"study":[120],"scaling":[125],"on":[126],"with":[129],"consideration":[130],"pipelining.For":[133],"sample":[135],"space,":[138],"can":[145],"increase":[146],"estimated":[148],"against":[150],"no-wire-pipelining":[152],"approach":[153],"between":[154],"25%":[155],"45%.":[157],"We":[158],"also":[159],"demonstrate":[160],"value":[162],"in":[166],"exploring":[167],"processor.":[173]},"counts_by_year":[{"year":2015,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}