{"id":"https://openalex.org/W2115315011","doi":"https://doi.org/10.1145/1120725.1120850","title":"A framework for automated and optimized ASIP implementation supporting multiple hardware description languages","display_name":"A framework for automated and optimized ASIP implementation supporting multiple hardware description languages","publication_year":2005,"publication_date":"2005-01-01","ids":{"openalex":"https://openalex.org/W2115315011","doi":"https://doi.org/10.1145/1120725.1120850","mag":"2115315011"},"language":"en","primary_location":{"id":"doi:10.1145/1120725.1120850","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1120725.1120850","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 conference on Asia South Pacific design automation  - ASP-DAC '05","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5036858189","display_name":"Oliver Schliebusch","orcid":null},"institutions":[{"id":"https://openalex.org/I99977706","display_name":"FH Aachen","ror":"https://ror.org/04tqgg260","country_code":"DE","type":"education","lineage":["https://openalex.org/I99977706"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Oliver Schliebusch","raw_affiliation_strings":["Aachen University of Technology, Aachen, Germany","Integrated Signal Process Syst., Aachen Univ. of Technol., Germany"],"affiliations":[{"raw_affiliation_string":"Aachen University of Technology, Aachen, Germany","institution_ids":["https://openalex.org/I99977706"]},{"raw_affiliation_string":"Integrated Signal Process Syst., Aachen Univ. of Technol., Germany","institution_ids":["https://openalex.org/I99977706"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089860351","display_name":"Anupam Chattopadhyay","orcid":"https://orcid.org/0000-0002-8818-6983"},"institutions":[{"id":"https://openalex.org/I99977706","display_name":"FH Aachen","ror":"https://ror.org/04tqgg260","country_code":"DE","type":"education","lineage":["https://openalex.org/I99977706"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"A. Chattopadhyay","raw_affiliation_strings":["Aachen University of Technology, Aachen, Germany","Integrated Signal Process Syst., Aachen Univ. of Technol., Germany"],"affiliations":[{"raw_affiliation_string":"Aachen University of Technology, Aachen, Germany","institution_ids":["https://openalex.org/I99977706"]},{"raw_affiliation_string":"Integrated Signal Process Syst., Aachen Univ. of Technol., Germany","institution_ids":["https://openalex.org/I99977706"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091010293","display_name":"David W. Kammler","orcid":null},"institutions":[{"id":"https://openalex.org/I99977706","display_name":"FH Aachen","ror":"https://ror.org/04tqgg260","country_code":"DE","type":"education","lineage":["https://openalex.org/I99977706"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"D. Kammler","raw_affiliation_strings":["Aachen University of Technology, Aachen, Germany","Integrated Signal Process Syst., Aachen Univ. of Technol., Germany"],"affiliations":[{"raw_affiliation_string":"Aachen University of Technology, Aachen, Germany","institution_ids":["https://openalex.org/I99977706"]},{"raw_affiliation_string":"Integrated Signal Process Syst., Aachen Univ. of Technol., Germany","institution_ids":["https://openalex.org/I99977706"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050903837","display_name":"Gerd Ascheid","orcid":"https://orcid.org/0000-0003-4068-3558"},"institutions":[{"id":"https://openalex.org/I99977706","display_name":"FH Aachen","ror":"https://ror.org/04tqgg260","country_code":"DE","type":"education","lineage":["https://openalex.org/I99977706"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"G. Ascheid","raw_affiliation_strings":["Aachen University of Technology, Aachen, Germany","Integrated Signal Process Syst., Aachen Univ. of Technol., Germany"],"affiliations":[{"raw_affiliation_string":"Aachen University of Technology, Aachen, Germany","institution_ids":["https://openalex.org/I99977706"]},{"raw_affiliation_string":"Integrated Signal Process Syst., Aachen Univ. of Technol., Germany","institution_ids":["https://openalex.org/I99977706"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023470562","display_name":"Rainer Leupers","orcid":"https://orcid.org/0000-0002-6735-3033"},"institutions":[{"id":"https://openalex.org/I99977706","display_name":"FH Aachen","ror":"https://ror.org/04tqgg260","country_code":"DE","type":"education","lineage":["https://openalex.org/I99977706"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"R. Leupers","raw_affiliation_strings":["Aachen University of Technology, Aachen, Germany","Integrated Signal Process Syst., Aachen Univ. of Technol., Germany"],"affiliations":[{"raw_affiliation_string":"Aachen University of Technology, Aachen, Germany","institution_ids":["https://openalex.org/I99977706"]},{"raw_affiliation_string":"Integrated Signal Process Syst., Aachen Univ. of Technol., Germany","institution_ids":["https://openalex.org/I99977706"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020992230","display_name":"H. Meyr","orcid":null},"institutions":[{"id":"https://openalex.org/I99977706","display_name":"FH Aachen","ror":"https://ror.org/04tqgg260","country_code":"DE","type":"education","lineage":["https://openalex.org/I99977706"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"H. Meyr","raw_affiliation_strings":["Aachen University of Technology, Aachen, Germany","Integrated Signal Process Syst., Aachen Univ. of Technol., Germany"],"affiliations":[{"raw_affiliation_string":"Aachen University of Technology, Aachen, Germany","institution_ids":["https://openalex.org/I99977706"]},{"raw_affiliation_string":"Integrated Signal Process Syst., Aachen Univ. of Technol., Germany","institution_ids":["https://openalex.org/I99977706"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074500359","display_name":"Tim Kogel","orcid":"https://orcid.org/0000-0002-7397-2615"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Tim Kogel","raw_affiliation_strings":["CoWare, Inc., San Jose, CA"],"affiliations":[{"raw_affiliation_string":"CoWare, Inc., San Jose, CA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5036858189"],"corresponding_institution_ids":["https://openalex.org/I99977706"],"apc_list":null,"apc_paid":null,"fwci":3.9571,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.93554366,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"280","last_page":"280"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8663066625595093},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.7011504173278809},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.6016522645950317},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.5862947702407837},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5577088594436646},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5502979755401611},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.48587340116500854},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.46972692012786865},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.4573899507522583},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.4571599066257477},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.4534851908683777},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.4206737279891968},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.399975061416626},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3552192449569702},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3329929709434509},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.31654834747314453},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.24605780839920044},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.2072398066520691},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.12949955463409424},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.11681506037712097}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8663066625595093},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.7011504173278809},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.6016522645950317},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.5862947702407837},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5577088594436646},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5502979755401611},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.48587340116500854},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.46972692012786865},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.4573899507522583},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.4571599066257477},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.4534851908683777},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.4206737279891968},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.399975061416626},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3552192449569702},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3329929709434509},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.31654834747314453},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.24605780839920044},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2072398066520691},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12949955463409424},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.11681506037712097},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1120725.1120850","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1120725.1120850","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 conference on Asia South Pacific design automation  - ASP-DAC '05","raw_type":"proceedings-article"},{"id":"pmh:oai:publications.rwth-aachen.de:125889","is_oa":false,"landing_page_url":"https://publications.rwth-aachen.de/record/125889","pdf_url":null,"source":{"id":"https://openalex.org/S4306401362","display_name":"RWTH Publications (RWTH Aachen)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I887968799","host_organization_name":"RWTH Aachen University","host_organization_lineage":["https://openalex.org/I887968799"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Proceedings of the ASP-DAC 2005, Asia and South Pacific Design Automation Conference 2005 : January 18 - 21, 2005, Hotel Equatorial, Shanghai, China / sponsored by: Chinese Institute of Electronics. Co-sponsored by: IEEE Beijing Section ... Technically co-sponsored by: IEEE CAS .... - Vol. 1<br/>Asia and South Pacific Design Automation Conference 2005, ASP-DAC 2005, Shanghai, Peoples R China, 2005-01-18 - 2005-01-21","raw_type":"info:eu-repo/semantics/publishedVersion"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W42428600","https://openalex.org/W1568871614","https://openalex.org/W1585971644","https://openalex.org/W1954375898","https://openalex.org/W1957956207","https://openalex.org/W1994143452","https://openalex.org/W2000801758","https://openalex.org/W2014714034","https://openalex.org/W2055511200","https://openalex.org/W2091788277","https://openalex.org/W2112537029","https://openalex.org/W2137474858","https://openalex.org/W2138362897","https://openalex.org/W2156088664","https://openalex.org/W2161038820","https://openalex.org/W2534549903"],"related_works":["https://openalex.org/W4281926497","https://openalex.org/W2269990635","https://openalex.org/W2108242004","https://openalex.org/W2042762783","https://openalex.org/W4283730710","https://openalex.org/W4281784598","https://openalex.org/W2921149022","https://openalex.org/W1536721241","https://openalex.org/W2101694480","https://openalex.org/W2556823985"],"abstract_inverted_index":{"Architecture":[0],"Description":[1],"Languages":[2],"(ADLs)":[3],"are":[4,69,96],"widely":[5],"used":[6],"to":[7,42,57,72,104,131,138],"perform":[8,73],"design":[9,21],"space":[10,22],"exploration":[11,23],"for":[12],"Application":[13],"Specific":[14],"Instruction":[15],"Set":[16],"Processors":[17],"(ASIPs).":[18],"While":[19],"the":[20,35,52,77,83,86,128],"is":[24,40,54,127,150],"well":[25],"supported":[26],"by":[27],"numerous":[28],"tools":[29,68],"providing":[30],"high":[31],"flexibility":[32],"and":[33,101,137],"quality,":[34],"methodology":[36],"of":[37,85,147],"automated":[38],"implementation":[39],"limited":[41],"simple":[43],"transformations.":[44],"Assuming":[45],"fixed":[46],"architectural":[47],"templates,":[48],"information":[49],"given":[50],"in":[51,152],"ADL":[53],"directly":[55],"mapped":[56],"a":[58,153],"hardware":[59,141],"description":[60,117,142],"on":[61,120],"Register":[62],"Transfer":[63],"Level":[64],"(RTL).":[65],"Gate-Level":[66],"synthesis":[67,113],"not":[70],"able":[71],"potential":[74],"optimizations,":[75],"as":[76,90],"computational":[78],"complexity":[79],"grows":[80],"exponential":[81],"with":[82],"size":[84],"architecture.":[87],"Information":[88],"such":[89],"exclusiveness,":[91],"parallelism":[92],"or":[93],"boolean":[94],"relations":[95],"spread":[97],"over":[98],"multiple":[99],"modules":[100],"therefore":[102],"hard":[103],"determine.":[105],"In":[106],"this":[107],"paper,":[108],"we":[109],"present":[110],"an":[111,121],"ASIP":[112],"approach":[114,149],"from":[115],"architecture":[116],"languages,":[118],"based":[119],"Intermediate":[122],"Representation":[123],"(IR).":[124],"The":[125,145],"IR":[126],"key":[129],"technology":[130],"provide":[132],"new":[133],"language-independent":[134],"high-level":[135],"optimizations":[136],"realize":[139],"different":[140],"language":[143],"backends.":[144],"feasibility":[146],"our":[148],"proven":[151],"case-study.":[154]},"counts_by_year":[],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
