{"id":"https://openalex.org/W2136397546","doi":"https://doi.org/10.1145/1120725.1120845","title":"Post-layout logic duplication for synthesis of domino circuits with complex gates","display_name":"Post-layout logic duplication for synthesis of domino circuits with complex gates","publication_year":2005,"publication_date":"2005-01-01","ids":{"openalex":"https://openalex.org/W2136397546","doi":"https://doi.org/10.1145/1120725.1120845","mag":"2136397546"},"language":"en","primary_location":{"id":"doi:10.1145/1120725.1120845","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1120725.1120845","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 conference on Asia South Pacific design automation  - ASP-DAC '05","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108484594","display_name":"Aiqun Cao","orcid":null},"institutions":[{"id":"https://openalex.org/I1335490905","display_name":"Synopsys (Switzerland)","ror":"https://ror.org/03mb54f81","country_code":"CH","type":"company","lineage":["https://openalex.org/I1335490905","https://openalex.org/I4210088951"]},{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["CH","US"],"is_corresponding":true,"raw_author_name":"Aiqun Cao","raw_affiliation_strings":["Synopsys, Inc., Mountain View, CA","Synopsys, Inc. Mountain View, CA USA"],"affiliations":[{"raw_affiliation_string":"Synopsys, Inc., Mountain View, CA","institution_ids":["https://openalex.org/I4210088951"]},{"raw_affiliation_string":"Synopsys, Inc. Mountain View, CA USA","institution_ids":["https://openalex.org/I1335490905"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100820944","display_name":"Ruibing Lu","orcid":null},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]},{"id":"https://openalex.org/I1335490905","display_name":"Synopsys (Switzerland)","ror":"https://ror.org/03mb54f81","country_code":"CH","type":"company","lineage":["https://openalex.org/I1335490905","https://openalex.org/I4210088951"]}],"countries":["CH","US"],"is_corresponding":false,"raw_author_name":"Ruibing Lu","raw_affiliation_strings":["Synopsys, Inc., Mountain View, CA","Synopsys, Inc. Mountain View, CA USA"],"affiliations":[{"raw_affiliation_string":"Synopsys, Inc., Mountain View, CA","institution_ids":["https://openalex.org/I4210088951"]},{"raw_affiliation_string":"Synopsys, Inc. Mountain View, CA USA","institution_ids":["https://openalex.org/I1335490905"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110204557","display_name":"Cheng\u2010Kok Koh","orcid":null},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Cheng-Kok Koh","raw_affiliation_strings":["Purdue University, West Lafayette, IN","Purdue Univ., West LaFayette, IN"],"affiliations":[{"raw_affiliation_string":"Purdue University, West Lafayette, IN","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Purdue Univ., West LaFayette, IN","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5108484594"],"corresponding_institution_ids":["https://openalex.org/I1335490905","https://openalex.org/I4210088951"],"apc_list":null,"apc_paid":null,"fwci":0.7255,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.75577957,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"260","last_page":"260"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/domino-logic","display_name":"Domino logic","score":0.844935417175293},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.6872623562812805},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6757506132125854},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6314831376075745},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5811315178871155},{"id":"https://openalex.org/keywords/domino","display_name":"Domino","score":0.5358707904815674},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.5241092443466187},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5043255090713501},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.4783284664154053},{"id":"https://openalex.org/keywords/gene-duplication","display_name":"Gene duplication","score":0.4598051607608795},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.41782882809638977},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.33485978841781616},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.31712156534194946},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.19912496209144592},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14893239736557007},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.12418219447135925},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10256022214889526}],"concepts":[{"id":"https://openalex.org/C2777555262","wikidata":"https://www.wikidata.org/wiki/Q173391","display_name":"Domino logic","level":5,"score":0.844935417175293},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.6872623562812805},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6757506132125854},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6314831376075745},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5811315178871155},{"id":"https://openalex.org/C2776416436","wikidata":"https://www.wikidata.org/wiki/Q3751781","display_name":"Domino","level":3,"score":0.5358707904815674},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5241092443466187},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5043255090713501},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.4783284664154053},{"id":"https://openalex.org/C7602840","wikidata":"https://www.wikidata.org/wiki/Q746284","display_name":"Gene duplication","level":3,"score":0.4598051607608795},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.41782882809638977},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.33485978841781616},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.31712156534194946},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.19912496209144592},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14893239736557007},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.12418219447135925},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10256022214889526},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C161790260","wikidata":"https://www.wikidata.org/wiki/Q82264","display_name":"Catalysis","level":2,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1120725.1120845","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1120725.1120845","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 conference on Asia South Pacific design automation  - ASP-DAC '05","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.151.2923","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.151.2923","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://dynamo.ecn.purdue.edu/~chengkok/papers/2005/p260-cao.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2012601799","https://openalex.org/W2025555754","https://openalex.org/W2075265327","https://openalex.org/W2113386515","https://openalex.org/W2113538389","https://openalex.org/W2149966501","https://openalex.org/W2171155658"],"related_works":["https://openalex.org/W2534190481","https://openalex.org/W2171918386","https://openalex.org/W2118487491","https://openalex.org/W1894566516","https://openalex.org/W2139625229","https://openalex.org/W2158157809","https://openalex.org/W3042080464","https://openalex.org/W2155174752","https://openalex.org/W2991771859","https://openalex.org/W321873635"],"abstract_inverted_index":{"Logic":[0],"duplication":[1,30,44,53],"to":[2],"resolve":[3],"the":[4,52],"logic":[5,12,29,43],"reconvergent":[6],"paths":[7],"problem":[8],"encountered":[9],"in":[10,16,67],"Domino":[11,37],"synthesis":[13],"is":[14,45,55],"expensive":[15],"terms":[17],"of":[18],"area":[19],"and":[20,32,70],"power.":[21],"In":[22],"this":[23],"paper,":[24],"we":[25],"propose":[26],"a":[27,48],"combined":[28],"minimization":[31],"technology":[33],"mapping":[34],"scheme":[35],"for":[36],"circuits":[38],"with":[39],"complex":[40],"gates.":[41],"The":[42],"performed":[46],"as":[47,51],"post-layout":[49],"step":[50],"cost":[54],"minimized":[56],"based":[57],"on":[58],"accurate":[59],"timing":[60],"information.":[61],"Experimental":[62],"results":[63],"show":[64],"significant":[65],"improvements":[66],"area,":[68],"power,":[69],"delay.":[71]},"counts_by_year":[],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}